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The proper CPU ID for those Exynos variants is 0x5422,
but before the 0x5800 was set. This commit fix this back.
Changes:
- set cpu id to 0x5422 instead of 0x5800
- remove macro proid_is_exynos5800()
- add macro proid_is_exynos5422()
- change the calls to proid_is_exynos5800() with new macro
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This platform is based on Exynos5800 but the cpu id is 0x5422.
This doesn't fit the common Exynos SoC name convention, so now,
the CPU name is defined by device tree string, to be printed
properly.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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The CPU name for Exynos was concatenated with cpu id,
but for new Exynos platforms, like Chromebook Peach Pi
based on Exynos5800, the name of SoC variant does not
include the real SoC cpu id (0x5422).
For such case, the CPU name should be defined in device tree.
This commit introduces new device-tree property for Exynos:
- "cpu-model" - with cpu name string
If defined, then the cpu id is not printed.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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The function get_board_type() is called in two places by common code,
but the returned pointer was never check.
This commit adds checking the returned pointer, before use it.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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As sama5 board has 32k sram size, so the at91bootstrap and spl for sama5
boards is bigger than 16k (0x4000). That will overlap the U-Boot
environment. So I move environment to 0x6000. And reduce its size as
well.
Following shows the size of the spl binaries (v2015.04 vs v2015.07):
% ls v2015.04/*spi*spl.bin -l | awk '{print $5,$(NF)}'
15540 v2015.04/at91sam9n12ek_spiflash_defconfig_u-boot-spl.bin
15704 v2015.04/at91sam9x5ek_spiflash_defconfig_u-boot-spl.bin
16064 v2015.04/sama5d3xek_spiflash_defconfig_u-boot-spl.bin
16304 v2015.04/sama5d4ek_spiflash_defconfig_u-boot-spl.bin
16304 v2015.04/sama5d4_xplained_spiflash_defconfig_u-boot-spl.bin
% ls v2015.07/*spi*spl.bin -l | awk '{print $5,$(NF)}'
16136 v2015.07/at91sam9n12ek_spiflash_defconfig_u-boot-spl.bin
16300 v2015.07/at91sam9x5ek_spiflash_defconfig_u-boot-spl.bin
16664 v2015.07/sama5d3xek_spiflash_defconfig_u-boot-spl.bin
16904 v2015.07/sama5d4ek_spiflash_defconfig_u-boot-spl.bin
16904 v2015.07/sama5d4_xplained_spiflash_defconfig_u-boot-spl.bin
The gcc version is: gcc 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1)
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Bo Shen <voice.shen@gmail.com>
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Add 32bpp framebuffer support for the Atmel HLCDC driver. This is
needed for output bpp higher than 16bpp.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Global variables are bad. Get rid of this particular one, so we can
correctly instantiate multiple atmel mci interfaces, without having
them interfere with one another.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Instead of passing just the register area as a private data, introduce
a proper struct atmel_mci_priv structure instead. This will become useful
in the subsequent patch, where we eliminate the global variable from this
driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fix free()]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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After silencing the prints which were generated when reconfiguring the
clock of the SD/MMC bus, surprisingly, the driver stopped working such
that every attempt to use the SD/MMC bus caused the CPU to get totally
stuck hard. It turns out that the prints generated a short delay, which
was necessary for the CPU to reconfigure the clock without getting stuck.
Thus, this patch adds a short delay after the clock configuration instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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This driver generates clearly debugging prints when changing clock
speed, so silence those. Furthermore, the driver generates further
prints in case a command fails to complete. The later case woud be
useful, but for eMMC, command 8 can fail and it's not an error but
a part of the specification. Thus, make this debug() as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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crt0.S do both memset the bss section and call board_init_r for us, so
remove them from board_init_f().
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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At present the debug UART is not selected which causes a build error.
Correct this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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As more features are added for SD boot on LS1021A QDS board,
the size of U-Boot is larger. CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS
needs to be adjusted to a suitable value.
Starting address of the malloc pool used in SPL needs to be
adjusted too, or it will occupy the address u-boot loads.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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I2C1 can work on ls102xa rev2.0 SD boot, so add
ID EEPROM for SD boot.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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It will take more than 1s when wake up from deep sleep. Most of the
time is spent on outputing information. This patch reduced the deep
sleep latency by:
1. avoid outputing system informaton
2. remove flush cache after DDR restore
3. skip reloading second stage uboot binary when SD boot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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The ITS bit was being read incorrectly beacause of operator
precedence. The same ahs been corrected.
Signed-off-by: Lawish Deshmukh <lawish.deshmukh@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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SR_IE(Self-refresh interrupt enable) is needed for
Hardware Based Self-Refresh. Make it configurable and let
board code handle the rest.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Reviewed-by: York Sun <yorksun@freescale.com>
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Add secure boot support for mx7dsabresd target board
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Add mx7 secure boot support, add helper macro IS_HAB_ENABLED_BIT
to get the corresponding bit mask per SoC (mx7 or mx6) to identify
if securue boot feature is enabled/disabled.
On authenticate_image only check for mmu enabled on mx6 SoC to
force pu_irom_mmu_enabled so ROM code can perform mmu cache flush
mx7 SoC ROM code does not have this issue as ROM enables cache support
based on fuse settings.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Use read_fuse api fuction call to read secure boot fuse
settings (enabled/disabled).
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Add secure boot fuse details (location) bank = 1, word = 3;
for imx7 SoC platforms.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Add secure boot fuse details (location) bank = 0, word = 6;
for imx6 SoC platforms.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Add secure boot fuse helper struct to abstract the way
to find out secure boot settings per SoC iMX family
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Rework unified section macro select via Kconfig option
instead of macro definition in mx7_common header file.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target
platforms to resolve corresponding HAB_RVT_BASE base address,
the RVT table contains pointers to the HAB API functions in
ROM code.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Rework secure boot support for imx6, move existing hab support
for imx6 into imx-common for SoC reuse.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Move common chip revision id's to main cpu header file
mx25 generic include cpu header for chip revision
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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Add i.MX6DQP-Sabresd board support:
1. set fdt_file according to board_rev which is set at runtime.
2. Add mx6dqp_ddr_ioregs and calibration value for this board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
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This macro is not needed, since gd->ram_size is assigned value using
function imx_ddr_size().
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
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add FIT image support for the flea3 board.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Linux only boots IMX.51-based boards with device tree, so this board
would benefit from supporting it.
Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Cc: Stefano Babic <sbabic@denx.de>
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setting the gpr 1,8 and 12 registers to a fix value.
This is needed because after a WDT reset, this registers
are not correct resettet, and prevent linux from booting
again.
Signed-off-by: Heiko Schocher <hs@denx.de>
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add some missing gpr register defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Add MXC_OCOTP Kconfig entry.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
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We can reuse common functions in lib/time.c, but not reimplement
functions in imx-common/time.c.
Only keep timer_init ,get_tbclk and implement timer_read_counter in
imx-common/time.c.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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eth_get_dev() can return NULL which means device_probe() fails for
that ethernet device. Add return value check in various places or
U-Boot will crash due to NULL pointer access.
With this commit, 'dm_test_eth_act' test case passes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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U-Boot crashes when doing a 'ping' with the following test scenario:
- All ethernet devices are not probed
- "ethaddr" for all ethernet devices are not set
- "ethact" is set to a valid ethernet device name
Add a new test case 'dm_test_eth_act' to hit such scenario.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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platdata->enetaddr was assigned to a value in dev_probe() last time.
If we don't clear it, for dev_probe() at the second time, dm eth
will end up treating it as a MAC address from ROM no matter where it
came from originally (maybe env, ROM, or even random). Fix this by
clearing platdata->enetaddr when removing an Ethernet device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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dev->uclass->uc_drv->per_device_auto_alloc_size is to be freed in
device_free(), so is dev->seq. Remove these unnecessary codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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In pch_gbe_probe(), some additional resources are allocated
(eg: mdio, phy). We should free these in the driver remove phase.
Add pch_gbe_remove() to clean it up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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In designware_eth_probe(), some additional resources are allocated
(eg: mdio, phy). We should free these in the driver remove phase.
Add designware_eth_remove() to clean it up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Currently there is no API to uninitialize mdio. Add two APIs for this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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In phy_connect_dev(), if the phy device has an accociated mac device
before, a warning message will be printed. But we should test the
old device against the new one, if they are actually the same one,
don't print the warning message.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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In get_phy_device_by_mask(), when no phy is found, currently we only
print a message to show the first phy address that is not found. But
this is not always the case as multiple phys can be specified by
phy_mask. Change to print all phys that are not found, and to reduce
the console boot log, change to use 'debug' instead of 'printf'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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In get_phy_device_by_mask(), when no phy is found, we should not
create any phy device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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NAND-tree is used to check wiring between MAC and PHY using NAND gates
on the PHY side, hence the name.
NAND-tree initial status is latched at reset by probing the IRQ pin.
However some devices are sharing the PHY IRQ pin with other peripherals
such as Atmel SAMA5D[34]x-EK boards when using the optional TM7000
display module, therefore they are switching the PHY in NAND-tree test
mode depending on the current IRQ line status at reset.
This patch ensure PHY is not in NAND-tree test mode only for the Micrel
KSZ8051 PHY used by Atmel. There are other Micrel PHY affected but I
doubt they are used on such weird hardware design.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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