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path: root/arch/arm/cpu/armv7/exynos/clock.c
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2013-07-16arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.Łukasz Majewski
Provide proper setting for the APLL fout frequency calculation for Exynos4 based targets (especially Exynos4210 - Trats board). Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2013-07-09arm: exynos: fix clock calculationMinkyu Kang
There are differnce with clock calcuation by cpu variations. This patch will fix it according to user manual. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
2013-06-13EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results.Amar
This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk(). Signed-off-by: Amar <amarendra.xt@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-05-21Exynos5: clock: Update the equation to calculate PLL output frequencyAkshay Saraswat
According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: pwm: Remove dead code of function exynos5_get_pwm_clkAkshay Saraswat
As we shall now be using clock_get_periph_rate function. We find no reason for keeping code in function exynos5_get_pwm_clk. Hence, removing it. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: pwm: Use generic api to get pwm clk freqPadmavathi Venna
Use generic api to get the pwm clock frequency Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: clock: Add generic api to get the clk freqPadmavathi Venna
Add generic api to get the frequency of the required peripherial. This API gets the source clock frequency and returns the required frequency by dividing with first and second dividers based on the requirement. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-11Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clkJaehoon Chung
Mobile storage is used the CLK_DIV_FSYS3 value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-11Exynos: clock: support get_mmc_clk for exynosJaehoon Chung
To get exactly clock value for mmc, support the get_mmc_clk() like set_mmc_clk(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-01-10EXYNOS5: Change parent clock of FIMD to MPLLAjay Kumar
With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-26EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequencyChander Kashyap
Adds functions to extract clock frequency of Exynos4x12 IPs. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-12-22Merge samsung, imx, tegra into u-boot-arm/masterAlbert ARIBAUD
This commit merges branches from samsung, imx and tegra meant to fix merge issues between u-boot/master and u-boot-arm/master, as well as a few manual merge fixes.
2012-12-19Merge remote-tracking branch 'u-boot/master' into u-boot-arm-mergedAllen Martin
Conflicts: README arch/arm/cpu/armv7/exynos/clock.c board/samsung/universal_c210/universal.c drivers/misc/Makefile drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/seaboard.h
2012-12-11exynos:clock: Add i2c clockPiotr Wilczek
This patch adds i2c clock for Exynos4 Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15EXYNOS: Add clock for SPIHatim RV
Add api to calculate and set the clock for SPI channels Signed-off-by: James Miller <jamesmiller@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15EXYNOS: Add clock for I2SRajeshwari Shinde
This patch adds clock support for I2S Signed-off-by: R. Chandrasekar <rcsekar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-11-15EXYNOS: Clock: Add common function for pll rate calculationMinkyu Kang
Moved the common code to calculate pll clock rate to new function exynos_get_pll_clk(). Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
2012-09-01EXYNOS5: support exynos5 lcd clock controlDonghwa Lee
This patch support exynos5 lcd clock control. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01ARM: EXYNOS: fixed compiler warning messageJaehoon Chung
Removed [-Wuninitialized] warning message. The fout_sel is assigned to "-1" by default. And start, gpio_func is initialized to 0. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01EXYNOS5: CLOCK: Add BPLL supportRajeshwari Shinde
This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0Rajeshwari Shinde
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-07-31EXYNOS: CLK: Add i2c clockRajeshwari Shinde
This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
2012-05-15EXYNOS: add LCD and MIPI DSI clock interface.Donghwa Lee
To sets up lcd and mipi clock in EXYNOS display driver, added clock interface. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12ARM: EXYNOS: Add support for Exynos5 based SoCsChander Kashyap
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macroChander Kashyap
CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12Exynos: Fix ARM Clock frequency calculationChander Kashyap
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calculating it as follows: ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1) Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-12-09S5PC2XX: Rename S5pc2XX to exynosChander Kashyap
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15 based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15 based SoC's will be sub-classified as Exynos4 and Exynos5 respectively. In order to better adapt and reuse code across various upcoming Samsung Exynos based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix are renamed as exynos4/EXYNOS4. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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