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2012-02-12OMAP4: clock-common: Move the usb dppl configuration to new funcGovindraj.R
usb dpll configuration is done only part of non-essential dppl configuration however if CONFIG_USB_EHCI_OMAP is defined we may have to configure usb dpll's for proper functioning of usb modules. So move the usb dppl configuration to a new func. and utilise the same during essential dpll configuration. Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
2012-02-12OMAP3+: Clock: Adding ehci clock enablingGovindraj.R
Adding ehci clock enabling mechanism part of clock framework. When essential clocks are enabled during init phase usb host clocks can also be enabled from clock framework. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
2012-02-12ARM: EXYNOS: Add support for Exynos5 based SoCsChander Kashyap
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macroChander Kashyap
CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12S5P: support generic watchdog timerMinkyu Kang
This patch adds support the generic watchdog timer for s5pc1xx and exynos4 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: HeungJun, Kim <riverful.kim@samsung.com>
2012-02-12Exynos: Fix ARM Clock frequency calculationChander Kashyap
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calculating it as follows: ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1) Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-02-12i.mx: i.mx5: update imx_get_mac_from_fuse functionJason Liu
FEC does not work on the i.mx51/53evk board, it will hangup In: serial Out: serial Err: serial Net: After bisect, it due to the following commit: be252b6 net: imx: Add multi-FEC support for imx_get_mac_from_fuse has change the imx_get_mac_from_fuse fucntion prototype, but fail to update i.mx5, here it does it. After apply this patch, u-boot works again on i.mx51/53 evk boards. Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-02-12OMAP SPL: Fix missing timer_init() call in OMAP4 s_init()Dechesne, Nicolas
In 8775471bb, the call to timer_init() was removed from common code and put in OMAP3 s_init() function. As a result the boot was broken on OMAP4. This patch adds timer_init() in OMAP4 s_init(), that fix boot on all OMAP4 boards. Signed-off-by: Nicolas Dechesne <n-dechesne@ti.com> Tested-by: Robert P. J. Day <rpjday@crashcourse.ca> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <trini@ti.com>
2012-02-12OMAP3: Correct get_sdr_cs_offset maskTom Rini
The function get_sdr_cs_offset reads the CS_CFG register in the SDRC to determine where CS1 is mapped to. make_cs1_contiguous() will set CS1 to follow after CS0. The CS_CFG register has values in bits 9:8 and 3:0 but we had erroneously been testing 5:4 and 3:0 resulting in incorrect offsets on platforms with less than 128MB as 3:0 describe 128MB hunks and 9:8 describe 32MB offsets after the 128MB hunk. Tested-by: Grant Erickson <marathon96@gmail.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-02-12arm: omap3: Define save_boot_params in lowlevel_init.S for SPL onlyPali Rohár
Wrap the function save_boot_params with CONFIG_SPL_BUILD. This will allow non-SPL boards to define their own save_boot_params functions in U-Boot itself. Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
2012-02-12tegra2: Enable data cacheSimon Glass
This enables the data cache on Tegra2 boards. As discussed on the list, this is better off in the Tegra2 cpu code than in a particular vendor directory. We should be safe turning on the cache for all Tegra2 boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12tegra: Add SDMMC support to funcmuxSimon Glass
This adds support for SDMMC ports to the funcmux. Only one option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit wide SDIO interface where available. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12tegra: Add I2C support to funcmuxSimon Glass
Add support to funcmux for selecting I2C functions and programming the pinmux appropriately. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12tegra: Add enum to select from available funcmux configsSimon Glass
We want to give a name to each available funcmux config. For now we just use the pin group names (even through it is verbose) since there seems to be nothing better. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12tegra: Adjust funcmux config test to permit expansionSimon Glass
We want to support config options other than zero, so move the test to the end to allow intermediate code to OK such a config. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12tegra2: Fix default RAM size selection in odmdataStephen Warren
A value of 0 in the odmdata RAM size field means default, which is 512MB not 1GB. Fix this. For reference, see: http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;\ f=arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h;\ h=1ec7010911454f19a5018952fd245785a62c59ad;\ hb=0e52d7fe25b11a656c376a37890be219470661fb v2: New patch Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-02-12tegra2: Fix conflicting pinmux for UARTAStephen Warren
Tegra appears to boot with function UARTA pre-selected on mux group SDB. If two mux groups are both set to the same function, it's unclear which group's pins drive the RX signals into the HW module. For UARTA, SDB certainly overrides group IRTX in practice. To solve this, configure some alternative function on SDB to avoid the conflict. Also, tri-state the group to avoid driving any signal onto it until we know what's connected. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-01-23ARM: AM33XX: Add i2c supportPatil, Rachna
Add i2c driver board hookup for AM335X EVM Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Patil, Rachna <rachna@ti.com>
2012-01-16omap_rev_string: output to stdoutAndreas Müller
* avoid potential buffer overflows * allow SPL-build not to output "Texas Instruments Revision detection unimplemented" Signed-off-by: Andreas Müller <schnitzeltony@gmx.de> Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16OMAP SPL: call timer_init in s_init to make udelay work earlierAndreas Müller
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
2012-01-16ARM:AM33XX: Add SPL support for AM335X EVMChandan Nath
This patch is added to support SPL feature on AM335X platform. In this patch, MMC1 is configured as boot device for SPL and support for other devices will be added in the next patch series. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2012-01-16ARM:AM33XX: Add mmc/sd supportChandan Nath
This patch add supports for mmc/sd driver on AM335X platform. PLL and pinmux configurations for mmc/sd are configured in this patch. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16ARM:AM33XX: Fix ddr and timer register offsetChandan Nath
This patch is added to update incorrect ddr and timer register offset. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-01-16omap3: make get_board_rev() function weakNikita Kiryanov
Current get_board_rev() function returns a hard coded value which is obviously incorrect for the majority of boards. Allow boards to provide a correct implementation by making this function weak. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2012-01-16omap4: fix boot issue on ES2.0 PandaAneesh V
Fix boot issue on ES2.0 Panda by tuning some IO settings. The CONTROL_EFUSE_2 register has to be over-ridden in software for 4430 boards. Commit 23e9f0723e48615332119de4f4ec7a833a282628 wrongly did this for CONTROL_EFUSE_1. Reverting this and doing it for CONTROL_EFUSE_2. Signed-off-by: Aneesh V <aneesh@ti.com> Tested-by: Raúl Porcel <armin76@gentoo.org>
2012-01-16imx: mx6q: add aipstz init for off platform periphJason Liu
Init peripheral access control register of AIPSTZ OPACRx: Buffer Writes(BW): 0 -> not bufferable, Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses. Write Protect(WP): 0 -> allows write accesses. Trusted Protect(TP): 0 -> allows unstrusted master Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Stefano Babic <sbabic@denx.de>
2012-01-16i.mx6:imx6q: allign MAC address with burned-in orderingJason Liu
For the i.mx6q, the burned-in MAC address will be the following odering, fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5] fuse: 0x620[15:8] MAC_ADDR[15:8] ---> mac[4] fuse: 0x620[23:16] MAC_ADDR[23:16] ---> mac[3] fuse: 0x620[31:24] MAC_ADDR[31:24] ---> mac[2] fuse: 0x630[7:0] MAC_ADDR[39:32] ---> mac[1] fuse: 0x630[15:8] MAC_ADDR[47:40] ---> mac[0] This patch also fix the error caculation for the fuse bank[0] address Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Stefano Babic <sbabic@denx.de>
2012-01-16net: imx: Add multi-FEC support for imx_get_mac_from_fuseFabio Estevam
Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter. This feature is important on mx28 SoC for example that has two FEC ports. Cc: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16i.mx: i.mx6q: Add the enet clock functionJason Liu
Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jason Liu <jason.hui@linaro.org> Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-09gpio: Replace ARM gpio.h with the common API in include/asm-genericJoe Hershberger
ARM boards should use the generic GPIO API This means changing gpio to unsigned type Remove the unused gpio_toggle() function which is not part of the API Comment that free should not modify pin state Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> fixed merge conflict in da8xx_gpio.c, tegra2_gpio.c, and extended to the new mxs_gpio.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2011-12-24tegra: Add support for UART init in cpu board.cSimon Glass
We add a way of initialising the selected of UARTs prior to relocation. Boards can use the board_init_uart_f() instead of repeating this code themselves. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24tegra: Add a function mux featureSimon Glass
funcmux permits selection of config options for particular peripherals, such as the pins that are used for that peripheral, if there are several options. Add UART selection to start with. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24tegra: add clock_ll_start_uart() to enable UART prior to relocSimon Glass
Most boards will want to enable a UART early. This function provides that feature in Tegra architecture code so the code does not need to be copied on every board. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24tegra: Move clock_early_init() to arch_cpu_init()Simon Glass
The clock init is not board specific, so move it into the cpu code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24tegra: Move cpu_init_cp15() to arch_cpu_init()Simon Glass
This call is more of an architecture requirement than a board one, so move it there. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-24tegra2: Always build with USE_PRIVATE_LIBGCC=yes.Thierry Reding
The AVP on Tegra2 doesn't boot properly when U-Boot is linked against the GCC provided libgcc. To work around this, always build and link against a private libgcc for Tegra2-based boards. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-21arm: Tegra: fix undefined instruction hang immediately after resetTom Warren
commit 0d479b53 (Aneesh V) added code for OMAP4 that doesn't execute on Tegra, due to the AVP (ARM7TDI) not having a CP15. Result was an undefined instruction hang just after reset. Signed-off-by: Tom Warren <twarren@nvidia.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Aneesh V <aneesh@ti.com>
2011-12-11USB: MX5: add helper functions to enable USB clocksWolfgang Grandegger
Signed-off-by: Wolfgang Grandegger <wg@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Remy Bohmer <linux@bohmer.net> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Jason Liu <r64343@freescale.com> V2: Fix spacing in crm_regs.h
2011-12-09i.mx: add the initial support for freescale i.MX6Q processorJason Liu
i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor. Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc:Stefano Babic <sbabic@denx.de>
2011-12-09i.mx: introduce the armv7/imx-common folderJason Liu
In order to support the coming MX6 platform and to reducde the duplicated code, we had better move some common files or functions to the imx-common folder for sharing. This patch does the following: - move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c - move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature added but just fix the checkpatch errors in the old file and remove the CONFIG_SYS_MX5_CLK32 reference in the file - create one new file cpu.c file to store the common function with i.mx5/6 Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc:Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2011-12-09S5PC2XX: Rename S5pc2XX to exynosChander Kashyap
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15 based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15 based SoC's will be sub-classified as Exynos4 and Exynos5 respectively. In order to better adapt and reuse code across various upcoming Samsung Exynos based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix are renamed as exynos4/EXYNOS4. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2011-12-09tegra2: Don't use board pointer before it is set upSimon Glass
In board_init_f() the gd->bd pointer is not valid when dram_init() is called. This only avoids dying because DRAM is at zero on Tegra2. The common ARM routine sets up the banks in the same way anyway, so we can just remove this code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09tegra2: Remove unneeded 'dynamic ram size' messageSimon Glass
This message is not required, since it is followed by an 'official' U-Boot message. U-Boot 2011.03-00048-gd7cb0d3 (May 11 2011 - 17:17:23) TEGRA2 Board: NVIDIA Seaboard dynamic ram_size = 1073741824 DRAM: 1 GiB becomes: TEGRA2 Board: NVIDIA Seaboard DRAM: 1 GiB This is a separate commit since it changes behavior. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09tegra2: Remove unneeded boot codeSimon Glass
Since we have cache support built in we can remove Tegra's existing cache initialization code amd other related dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09arm: Move CP15 init out of cpu_init_crit()Simon Glass
Some SOCs have do not start up with their 'main' CPU. The first U-Boot code may then be executed with a CPU which does not have a CP15, or not a useful one. Here we split the initialization of CP15 into a separate call, which can be performed later if required. Once the main CPU is running, you should call cpu_init_cp15() to perform this init as early as possible. Existing ARMv7 boards which define CONFIG_SKIP_LOWLEVEL_INIT should not need to change, this CP15 init is still skipped in that case. The only impact for these boards is that the cpu_init_cp15() will be available even if it is never used on these boards. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09tegra2: Simplify tegra_start() boot pathSimon Glass
The Tegra2 boot path is more complicated than it needs to be. Since we want to move to building most of U-Boot with ARMv7 and only a small part with ARMv4T (for AVP) it should be as simple as possible. This makes tegra2_start() into a simple function which either does AVP init or A9 init depending on which core is running it. Both cores now following the same init path, beginning at _start, and the special Tegra2 boot path code is no longer required. Only two files need to be built for ARMv4T, and this is handled in the Tegra2 CPU Makefile. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-09tegra2: Add arch_cpu_init() to fire up Cortex-A9Simon Glass
We want to move away from a special Tegra2 start-up, and just use arch_cpu_init() instead. However, if we run board_init_f() from boot we need to build it for ARMv4T, since the Tegra's AVP start-up CPU does not support ARMv7. The effect of this is to do the AVP init earlier, and in arch_cpu_init(), rather that board_early_init_f(). Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-12-06arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warningsAnatolij Gustschin
Fix: clocks-common.c: In function 'setup_dplls': clocks-common.c:256:6: warning: variable 'sysclk_ind' set but not used [-Wunused-but-set-variable] clocks-common.c: In function 'setup_non_essential_dplls': clocks-common.c:292:6: warning: variable 'sysclk_ind' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Tom Rini <trini@ti.com>
2011-12-06arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warningsAnatolij Gustschin
Fix: spl.c: In function 'jump_to_image_no_args': spl.c:103: warning: assignment makes pointer from integer without a cast spl.c:105: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Tom Rini <trini@ti.com>
2011-12-06mx5: Correct a warning in clock.cSimon Glass
This corects the warning below, obtained with my gcc 4.6 compiler. arch/arm/cpu/armv7/mx5/libmx5.o: In function `decode_pll': arch/arm/cpu/armv7/mx5/clock.c:94: undefined reference to `__aeabi_uldivmod' I am not able to test this on MX5x hardware, but it does improve the MAKEALL output for me. You may already have a similar patch, but I cannot see it on the list. Signed-off-by: Simon Glass <sjg@chromium.org>
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