summaryrefslogtreecommitdiff
path: root/arch/arm/cpu/armv7
AgeCommit message (Collapse)Author
2014-01-17mx6: Revert "mx6: soc: Disable VDDPU regulator"Fabio Estevam
Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Reported-by: Pierre Aubert <p.aubert@staubli.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-15mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()Fabio Estevam
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-13imx6: make use of lldiv(..)Christian Gmeiner
Commit 762a88ccf8540948fbf8c31b40a29d1e0684a25b introduces a 64-bit division without using the lldiv() function, which pulls in previously unused libgcc stuff. Signed-off-by: Måns Rullgård <mans@mansr.com> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-06Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-01-06Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD
Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
2014-01-03arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin
Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2014-01-03ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6Otavio Salvador
The enable_fec_anatop_clock method should be available for all MX6 variant as it is not MX6 SoloLite specific. This moves the code out of the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-02mx6: soc: Disable VDDPU regulatorFabio Estevam
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02mx6: soc: Add the required LDO ramp up delayFabio Estevam
When changing LDO voltages we need to wait for the required amount of time for the voltage to settle. Also, as the timer is still not available when arch_cpu_init() is called, we need to call it later at board_postclk_init() phase. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02mx6: soc: Introduce set_ldo_voltage()Fabio Estevam
Introduce set_ldo_voltage() so that all three LDO regulators can be configured. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02mx6: soc: Set the VDDSOC at 1.175 VFabio Estevam
mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V. Add a 25 mV margin and set it to 1.175V. This also matches the VDDSOC voltages for 792MHz operation that the kernel configures: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltagesFabio Estevam
Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00: 00: 64 cycles of 24MHz clock; 01: 128 cycles of 24MHz clock; 02: 256 cycles of 24MHz clock; 03: 512 cycles of 24MHz clock; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-02mx6: soc: Staticize set_vddsoc()Fabio Estevam
set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-12-30Exynos5420: Add support for 5420 in pinmux and gpioRajeshwari Birje
Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje
This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-30Exynos5420: Add clock initialization for 5420Rajeshwari Birje
This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-18ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18ARM: AM33xx+: Update ioregs to pass different valuesLokesh Vutla
Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
2013-12-18ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla
Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-18ARM: AM43xx: Select clk source for Timer2Lokesh Vutla
Selecting the Master osc clk as Timer2 clock source. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-17imx6: fix random hang when download by usbFrank Li
ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
2013-12-17mx6: clock: Fix the calculation of PLL_ENET frequencyFabio Estevam
According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-12-12ARM: OMAP5: clocks: Update MPU settings for OPP_NOMLokesh Vutla
As per the latest 0.6 version of DM for OMAP5430 ES2.0, MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU should be locked at 2000MHz. Fixing the same and cleaning the previously used dpll values. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-12ARM: DRA7xx: Change clk divider settingLokesh Vutla
Commit "armv7: hw_data: change clock divider setting" updates the setting for m6 divider for 20MHz sys_clk frequency. But missed to update for other sys_clk frequencies. Doing the same. Reported-by: Rajendran, Vinothkumar <vinothr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-12arm: omap: abb: add missing includeNikita Kiryanov
ABB code uses LDELAY but does not include the header that provides its definition. Include the header. Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Nishanth Menon <nm@ti.com>
2013-12-12am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFFTom Rini
Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches. Signed-off-by: Tom Rini <trini@ti.com>
2013-12-10Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD
Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
2013-12-06ARM: align MVBAR on 32 byte boundaryMasahiro Yamada
The lower 5 bit of MVBAR is UNK/SBZP. So, Monitor Vector Base Address must be 32-byte aligned. On the other hand, the secure monitor handler does not need 32-byte alignment. This commit moves ".algin 5" directive to the correct place. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andre Przywara <andre.przywara@linaro.org> Acked-by: Andre Przywara <andre.przywara@linaro.org>
2013-12-06Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-12-06Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-12-06arm: omap3: Enable clocks for peripherals only if they are usedMichael Trimarchi
This patch change the per_clocks_enable() function used in OMAP3 code to enable peripherals clocks. Only required clock should be activated. So if the board use the uart(x) as a console we need to activate it. The Board's config should include define to enable every subsystem that the board use. For a complete list of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER should be checked. Right now the bootloader can enable and disable clocks for: uart(x) using CONFIG_SYS_NS16550 gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 } i2c bus using CONFIG_DRIVER_OMAP34XX_I2C. Not required gptimer(x) and mcbsp(x) for booting are disabled by default and are not supported by any define. Their activation need to included in the per_clocks_enable if the peripheral is included. Not booting board should enable the peripheral clock connected to their driver Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2013-12-06arm: exynos: adds ifdef for spi bootMinkyu Kang
This patch fix following errors and warnings spl_boot.c: In function 'exynos_spi_copy': spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function) spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function) spl_boot.c: In function 'copy_uboot_to_ram': spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable] spl_boot.c: At top level: spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function] Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-12-06Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD
2013-12-04pandaboard: 1/1] ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAMHardik Patel
Signed-off-by: Hardik Patel <hardik.patel@volansystech.com>
2013-12-04ARM: OMAP5+: Remove unnecessary EFUSE settingsLokesh Vutla
Certain EFUSE settings were recommended for the first four lots of OMAP5 ES1.0 silicon. These are not applicable for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings. Reported-by: Griffis, Brad <bgriffis@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-04ARM: DRA7xx: Add PRCM and Control information for SATARoger Quadros
Adds the necessary PRCM and Control register information for SATA on DRA7xx. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04ARM: OMAP5: Add SATA platform glueRoger Quadros
Add platform glue logic for the SATA controller. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04ARM: OMAP5: Add PRCM and Control information for SATARoger Quadros
Adds the necessary PRCM and Control register information for SATA on OMAP5. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04ARM: OMAP5: Add Pipe3 PHY driverRoger Quadros
Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is a driver for the Pipe3 PHY. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-12-04ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039SRICHARAN R
When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-12-04ARM: DRA: EMIF: Change DDR3 settings to use hw levelingSRICHARAN R
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-12-04am33xx: Stop modifying certain EMIF4D registersTom Rini
Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Matt Porter <matt.porter@linaro.org>
2013-12-04ARM: OMAP4: Fix bug in omap4470_volts structLubomir Popov
The struct incorrectly referenced SMPS1 for all three power domains. Fixed this by using SMPS2 and SMPS5 as appropriate. Add some comments and choose voltage values that correspond to voltage selection codes. Signed-off-by: Lubomir Popov <l-popov@ti.com>
2013-12-03socfpga: Adding Freeze Controller driverChin Liang See
Adding Freeze Controller driver. All HPS IOs need to be in freeze state during pin mux or IO buffer configuration. It is to avoid any glitch which might happen during the configuration from propagating to external devices. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2013-12-03exynos: spl: Add a custom spi copy functionRajeshwari Shinde
This patch implements a custom spi_copy funtion to copy u-boot from SF to RAM. This is faster then iROM spi_copy funtion as this runs spi at 50Mhz and also in WORD mode of operation. Changed a printf in pinmux.c to debug just to avoid the compilation error in SPL. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-12-03arm: rmobile: Remove config.mkNobuhiro Iwamatsu
Renesas ARM SoCs (R-Mobile, R-Car) are armv7 only. This drops armv5 supprt from PLATFORM_CPPFLAGS and remove config.mk of rmobile. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-12-03arm: kzm9g: Fix undefined reference to `__aeabi_uldivmod' errorNobuhiro Iwamatsu
The kzm9g board fails in building with -march=armv7-a. This fixs this problem by converting to do_div(). ----- USE_PRIVATE_LIBGCC=yes ./MAKEALL kzm9g ... arch/arm/cpu/armv7/rmobile/librmobile.o: In function `get_time_us': arch/arm/cpu/armv7/rmobile/timer.c:41: undefined reference to `__aeabi_uldivmod' arch/arm/cpu/armv7/rmobile/librmobile.o: In function `get_time_ms': arch/arm/cpu/armv7/rmobile/timer.c:47: undefined reference to `__aeabi_uldivmod' ----- Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
2013-12-03arm: rmobile: Add support R8A7791Nobuhiro Iwamatsu
Renesas R8A7791 is CPU with Cortex-A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
2013-12-03arm: rmobile: Add support R8A7790Nobuhiro Iwamatsu
Renesas R8A7790 is CPU with Cortex-A7 and A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
generated by cgit (git 2.34.1) at 2025-01-15 08:04:50 +0000