summaryrefslogtreecommitdiff
path: root/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
AgeCommit message (Collapse)Author
2019-03-03armv8: fsl-layerscape: fix SEC QI ICID setupLaurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset that is being added to the ICID coming from the qman portal. Setting it with a non-zero value breaks SMMU setup as the resulting ICID is not known. On top of that, the SEC QI ICID must match the qman portal ICIDs in order to share the isolation context. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2018-09-27armv8: ls1043a: add icid setup supportLaurentiu Tudor
Reuse the existing ICID setup code done for LS1046A smmu enablement and add the equivalent setup for LS1043A chips. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>