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path: root/arch/arm/cpu/armv8/fsl-lsch3
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2015-07-20armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.Zhichun Hua
When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085a: Enable DSPI get input clk form 'mxc_get_clock'Haikun Wang
Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/fsl-lsch3: device tree fixups for PCI stream IDsStuart Yoder
This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085a: Update SoC README for DDR layoutPrabhakar Kushwaha
Update SoC README to provide details of - Memory regions - Memory used by MC and Debug server Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/fsl-ch3: Add support to print SoC personalityPrabhakar Kushwaha
This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/fsl-lsch3: Fix DDR speed messageYork Sun
DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
2015-07-20armv8/ls2085a: call ft_pcie_setup() to change dts statusPrabhakar Kushwaha
call ft_pci_setup() to disable PCIe dts node if corresponding PCIe controller is disabled according to RCW Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/fsl-lsch3: Implement workaround for I2C erratum A009203York Sun
This erratum requires setting GLITCH_EN bit in debug register to enable digital filter to improve clock stability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Heiko Schocher <hs@denx.de>
2015-04-23ls2085a: esdhc: Add esdhc support for ls2085aYangbo Lu
This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085ardb: Enable NAND SPL supportScott Wood
Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085aqds: NAND boot supportScott Wood
This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23driver/ifc: Add 64KB page supportJaiprakash Singh
IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085ardb: Add support of LS2085ARDB platformYork Sun
The LS2085ARDB is a evaluation platform that supports LS2085A family SoCs. This patch add sbasic support for the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-04-23armv8/ls2085aqds: Add support of LS2085AQDS platformYork Sun
The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2015-04-23driver/ldpaa: Add support of WRIOP static data structurePrabhakar Kushwaha
Wire rate IO Processor (WRIOP) provide support of receive and transmit ethernet frames from the ethernet MAC. Here Each WRIOP block supports upto 64 DPMACs. Create a house keeping data structure to support upto 16 DPMACs and store external phy related information. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/fsl-ch3: Add support to print RCW configurationBhupesh Sharma
This patch adds support to print out the Reset Configuration Word information. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23drivers/fsl-mc: Changed MC firmware loading for new boot architectureJ. German Rivera
Changed MC firmware loading to comply with the new MC boot architecture. Flush D-cache hierarchy after loading MC images. Add environment variables "mcboottimeout" for MC boot timeout in milliseconds, "mcmemsize" for MC DRAM block size. Check MC boot status before calling flib functions. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8: Add SerDes framework for Layerscape ArchitectureMinghuan Lian
Add support of SerDes framework for Layerscape Architecture. - Add support of 2 SerDes block - Add SerDes protocol parsing and detection - Create table of SerDes protocol supported by LS2085A Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/fsl-lsch3: Use correct compatible for serial clock fixupScott Wood
The serial nodes in the fsl-lsch3 device trees have compatible = "fsl,ns16550", "ns16550a" -- so don't look for "ns16550". Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085a: Add workaround for USB erratum A-008751Scott Wood
Without this "USB may not work" according to the erratum text, though I did not notice a problem without it. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23fsl-lsch3: Introduce place for common early SoC initScott Wood
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/fsl-lsch3: Update early MMU tableYork Sun
During booting, IFC is mapped to low region. After booting up, IFC is remapped to high region for larger space. The environmental variables are also stored at high region. In order to read the variables during booting, a virtual mapping is required. Cache was enabled for entire IFC space before. Actually the first two entries are big enough (4MB) to cover the boot code and environmental variables. Remove extra entries. Move OCRAM entry out of ifdef. Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/fsl-lsch3: Set nodes in DVM domainScott Wood
This is required for TLB invalidation broadcasts to work. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085a: Add support for reset requestpankaj chauhan
Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085a: Fix generic timer clock sourceYork Sun
The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
2015-04-23armv8/fsl-lsch3: Fix platform clock calculationYork Sun
Platform clock is half of platform PLL. There is an additional divisor in place. Clean up code copied from powerpc. Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-21driver/fsl-mc: Add support of MC FlibsPrabhakar Kushwaha
Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21fsl-ch3/README: Add description for NOR flash layout (firmware images)Bhupesh Sharma
This patch adds description for NOR flash layout (firmware images) in the README file for LS2085A platforms. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21armv8/fsl-lsch3: Add Freescale Debug Server driverBhupesh Sharma
The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24drivers/mc: Migrated MC Flibs to 0.5.2J. German Rivera
Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24armv8/fsl-lsch3: Add support for second DDR clockYork Sun
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks. Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodesBhupesh Sharma
This patch adds the fdt-fixup logic for the clock frequency of the NS16550A related device tree nodes. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun
Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24ARMv8/fsl-lsch3: Patch cpu node properties in DT for online coresArnab Basu
U-Boot should only add "enable-method" and "cpu-release-address" properties to the "cpu" node of the online cores. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24armv8/fsl-lsch3: Change normal memory shareabilityYork Sun
According to hardware implementation, a single outer shareable global coherence group is defined. Inner shareable has not bee enabled. Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accessesBhupesh Sharma
This patch ensures that the TZPC (BP147) and TZASC-400 programming happens for LS2085A SoC only when the desired config flags are enabled and ensures that the TZPC programming is done to allow Non-secure (NS) + secure (S) transactions only for DCGF registers. The TZASC component is not present on LS2085A-Rev1, so the TZASC-400 config flag is turned OFF for now. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-25armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot PageYork Sun
Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-07-04ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board supportYork Sun
LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2014-07-03armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera
Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
2014-07-03ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
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