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2019-10-24Merge branch '2019-10-24-UFS-support'Tom Rini
- Add Universal Flash Storage (UFS) support
2019-10-24arm: dts: k3-j721e-som-p0: Add HyperFlash nodeVignesh Raghavendra
J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2019-10-24arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller nodeVignesh Raghavendra
Add DT node for HyperBus Memory Controller in the FSS. On J721e, its not possible to use OSPI0 and HBMC simultaneously as they are muxed within the Flash Subsystem hence disable HBMC by default as keep OSPI enabled. Bootloader will fixup DT when it detects HyperFlash instead of OSPI. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2019-10-23arm: dts: k3-j721e-main: Add UFS nodesFaiz Abbas
Add TI UFS glue layer and Cadence UFS Host controller DT nodes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-18ARM: dts: meson-sm1: add U-Boot specific DT for graphicsNeil Armstrong
Rename meson-g12a-u-boot.dtsi into meson-g12-common-u-boot.dtsi to match the new DT architecture and add meson-sm1-sei610-u-boot.dtsi to handle the U-Boot specific DT for graphics. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18ARM: dts: Import SEI610 DT from Linux 5.4-rc2Neil Armstrong
Import the Amlogic SM1 DT and the SEI610 board DT from [1] [1] da0c9ea146cb ("Linux 5.4-rc2") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18arm: dts: Import and update DT for Khadas VIM3Andreas Färber
In Linux meson-g12-common.dtsi was introduced as well as new g12b nodes and headers, as dependencies of new meson-g12b-a311d-khadas-vim3.dts. Copied from da0c9ea146cb ("Linux 5.4-rc2") Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18ARM: dts: meson-g12a: add U-Boot specific DT for graphicsNeil Armstrong
Like the meson-gx support, add the U-Boot specific bits in DT to support graphics on G12A SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-14Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- vining_fpga updates
2019-10-14Merge tag 'u-boot-imx-20191014' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191014 ------------------- Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628 - logicpd pinmux - i.MX7ULP: imx_ddr_size - fixes Toradex i.MX6/i.MX7 - pico-imx7d - tpc70 converted to DM - New Board: meerkat96 - add HAB version command - i.MX8 : imx8: Jump from alias to OCRAM address at SPL init imx8qm/qxp: Set SPL TEXT base to OCRAM base
2019-10-13ARM: dts: stm32mp1: add dsi host for stm32mp157c-dk2 boardYannick Fertré
The new class dsi host allows the management of the bridge DPI to DSI. This bridge is embedded in the chipset mp1 (come from synopsys company). Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13ARM: dts: stm32mp1: add dsi host for stm32mp157c-ev1 boardYannick Fertré
The new class dsi host allows the management of the bridge DPI to DSI. This bridge is embedded in the chipset mp1 (come from synopsys company). Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13ARM: dts: stm32f769: add display for STM32F769 disco boardYannick Fertré
Enable the display controller, mipi dsi bridge & panel. Set panel display timings. Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13imx: dts: Add u-boot specific set of device tree properties for tpc70Lukasz Majewski
This commit adds new file - imx6q-kp-u-boot.dtsi with a set of u-boot specific properties for imx6q KP device. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-13imx: tpc70: dts: Add TPC70 board (imx6q based) device tree descriptionLukasz Majewski
This commit defines the TPC70 imx6q board with device tree description. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-13ARM: imx6q_logic: Enable Pin muxing in SPLAdam Ford
With the 256KB of OCRAM available to SPL now, there should be enough room to enable the pinmuxing in SPL from the device tree. This patch enables SPL_PINCTRL et al and adds the serial and usdhc pin mux references to the -u-boot.dtsi file so the pins can be configured from the device tree. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-13ARM: dts: imx6q-tbs2910: Sync devicetree with kernel 5.3Soeren Moch
Signed-off-by: Soeren Moch <smoch@web.de>
2019-10-13ARM: dts: import meerkat96 board supportShawn Guo
It imports device tree source of meerkat96 board from Linux Kernel. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-10-12Merge branch '2019-10-11-master-imports'Tom Rini
- Assorted cleanups - FAT bugfixes - mediatek platform updates
2019-10-11arm: dts: k3-j721e-common-proc-board: Mark main_uart0 as shared deviceLokesh Vutla
Main uart0 is used as debug console by both R5SPL and A72 bootloader and Linux. So mark it as shared device so that power-domain request is successful by both cores. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11board: ti: am335x-ice: Configure the CDCE913 clock synthesizerTero Kristo
AM335x-ICE boards contain the CDCE913 clock synthesizer, and their reset crystal capacitance load value of 10pF is wrong leading into lost packets in certain networking tests. Add DT data for this device, and probe it from the board file to program the crystal capacitance load value to 0pF to avoid any problems. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11board: ti: am43xx-idk: Configure the CDCE913 clock synthesizerTero Kristo
AM43xx-IDK boards contain the CDCE913 clock synthesizer, and their reset crystal capacitance load value of 10pF is wrong leading into lost packets in certain networking tests. Add DT data for this device, and probe it from the board file to program the crystal capacitance load value to 0pF to avoid any problems. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11board: ti: am57xx-idk: Configure the CDCE913 clock synthesizerTero Kristo
AM57xx-IDK boards contain the CDCE913 clock synthesizer, and their reset crystal capacitance load value of 10pF is wrong leading into lost packets in certain networking tests. Add DT data for this device, and probe it from the board file to program the crystal capacitance load value to 0pF to avoid any problems. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11am335x, guardian: adapt guardian board to DMMoses Christopher
- update partition table - remove env partitions - dts: add new interfaces (uart2, extra gpio-key) remove unneeded entries update nand timings for performance improvement - defconfig: adapt configurations to suit DM remove unneeded configs - am335x_guardian.h: remove mmc boot Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-10-11arm: dts: split mtk-reset.h into per-chip headerRyder Lee
This follows the linux header rules to avoid conflict bitfields. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11arm: dts: add PCIe controller for MT7623 SoCRyder Lee
This adds PCIe and its PHY nodes for MT7623. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11dt: bcm968580xref: add a spi-nor devicePhilippe Reynes
This commit add a spi-nor device in the bcm96850xref device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Kursad Oney <kursad.oney@broadcom.com>
2019-10-11dt: bcm6858: add hsspi controllerPhilippe Reynes
This commit add a hsspi controller in the bcm6858 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Kursad Oney <kursad.oney@broadcom.com>
2019-10-11dt: bcm963158: add a spi-nor deviceKursad Oney
This change adds a spi nor flash device to the bcm963158 board. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-11dt: bcm63158: Add hsspi controllerKursad Oney
This change adds the hsspi controller to the 63158 dtsi. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-11arm: dts: k3-am65-mcu: Add MCU domain R5F DT nodesSuman Anna
The AM65x SoCs has a single dual-core Arm Cortex-R5F processor subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-main: Add C71x DSP nodeLokesh Vutla
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN voltage domain containing the next-generation C711 CPU core. The subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of L2 configurable SRAM/Cache. This subsystem has a CMMU but is not used currently. The inter-processor communication between the main A72 cores and the C711 processor is achieved through shared memory and a Mailbox. Add the DT node for this DSP processor sub-system in the common k3-j721e-main.dtsi file. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-main: Add C66x DSP nodesLokesh Vutla
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs) in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional 288 KB of L2 configurable SRAM/Cache. These subsystems do not have an MMU but contain a Region Address Translator (RAT) sub-module for translating 32-bit processor addresses into larger bus addresses. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Add the DT nodes for these DSP processor sub-systems in the common k3-j721e-main.dtsi file. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-main: Add MAIN domain R5F cluster nodesLokesh Vutla
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for these two MAIN domain R5F cluster/subsystems, the two R5 cores are each added as child nodes to the corresponding main cluster node. Configure SS0 in split mode an SS1 in lockstep mode, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11arm: dts: k3-j721e-mcu: Add MCU domain R5F cluster nodeLokesh Vutla
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11armv7R: dts: k3: am654: Add MCU_UART0 related definitionsAndreas Dannenberg
Although we currently use the MAIN_UART0 for R5 SPL console output there are cases where we require access to the MCU_UART0 as well for example in case of UART-based Y-Modem boot. To support these scenarios add related DTS definitions to be able to use that UART early on. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-10-09ARM: socfpga: vining_fpga: Update DTMarek Vasut
Pick minor changes from the downstream DT, disable MMC, add GMAC0 node and adjust PHY skew settings for GMAC1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-10-09ARM: socfpga: vining_fpga: Rename VINING|FPGAMarek Vasut
The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-10-09Merge tag 'xilinx-for-v2020.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file
2019-10-09Merge tag 'u-boot-imx-20191009' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20191009 ------------------- Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/595148532 - MX6UL / ULZ - Toradex board - Allow to set OCRAM for MX6Q/D - MX7ULP - MX8: (container image, imx8mq_mek), SCU API - fix several board booting from SD/EMMC (cubox-i for example) - pico boards [trini: display5 merged manually] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-10-08pico-imx7d: Remove dead code for dm_videoJoris Offouga
Since convert dm_video, unused code introduced, so remove this Signed-off-by: Joris Offouga <offougajoris@gmail.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
2019-10-08imx: Add i.MX8MM EVK board support.Peng Fan
Add board and SoC dts Add ddr training code support SD/MMC/GPIO/PINCTRL/UART Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08arm: dts: add i.MX8MM pin funcPeng Fan
Import i.MX8MM pin func from Linux Kernel, commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08arm: dts: import i.MX8MM dtsiPeng Fan
Import i.MX8MM dtsi from Linux Kernel, commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add the i.MX8M reset controller nodePatrick Wildt
This patch adds the reset controller node to the i.MX8MQ SoC device tree. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-10-08imx: add support for i.MX8MQ power domain controllerPatrick Wildt
Add support for the power domain controller that's used on the i.MX8MQ. This will be needed to be able to power on the PCIe controller. Bindings taken from Linux, driver implementation taken from the i.MX8 power domain controller and adjusted for the i.MX8M SoC. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-10-08ARM: dts: pcl063: add usdhc reset pin of eMMCParthiban Nallathambi
pcl063 phycore SoM with eMMC also got usdhc reset pin, add reset pin to pinmux. Signed-off-by: Parthiban Nallathambi <pn@denx.de>
2019-10-08imx: wandboard: convert FEC support to DM_ETHAnatolij Gustschin
Remove CONFIG_DM_ETH conversion warning to avoid board removal. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-10-08dts: imx28: Remove #include "imx28.dtsi" from imx28-u-boot.dtsi fileLukasz Majewski
After this change it is possible to use imx28-<board>-u-boot.dtsi with the imx28-u-boot.dtsi explicitly included without breaking setup from imx28-<board>.dts file. The problem is that the imx28.dtsi included in a wrong place overrides the changes made in imx28-<board>.dts. As a result some devices are "disabled" in the final DTB. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-08DM: WDT: Convert WDT driver to use DM/DTS (including SYSRESET)Lukasz Majewski
This commit enables support for CONFIG_WDT in the U-Boot proper. Moreover, the SYSRESET_WATCHDOG driver is used to support 'reset' command. As SPL is not yet ready for DM conversion, the CONFIG_HW_WATCHDOG is enabled for it. This allows the legacy SPL code to work properly. Signed-off-by: Lukasz Majewski <lukma@denx.de>
generated by cgit (git 2.34.1) at 2025-01-10 17:36:10 +0000