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path: root/arch/arm/mach-imx/imx8m
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2020-03-09imx8mm/mn: Add missing root clock entry for ARM core clockFrieder Schrempf
The current implementation in arch/arm/mach-imx/cpu.c uses non-DM code to retrieve the core clock frequency. As the root clock is not listed we currently get: CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz Fix this by adding the missing entry, which results in: CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-02-09board: toradex: Add Verdin iMX8M Mini supportIgor Opaniuk
This adds initial minimal support for the Toradex Verdin iMX8M Mini Quad 2GB WB IT V1.0A module. They are now strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports booting from the on-module eMMC only, SDP support is disabled for now due to missing i.MX 8M Mini USB support. Functionality wise the following is known to be working: - eMMC, 8-bit and 4-bit MMC/SD card slots - Ethernet - GPIOs - I2C Boot sequence is: SPL ---> ATF (TF-A) ---> U-boot proper ATF, U-boot proper and u-boot.dtb images are packed into a FIT image, loaded by SPL. Boot: U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) Normal Boot Trying to boot from MMC1 NOTICE: Configuring TZASC380 NOTICE: RDC off NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty NOTICE: BL31: Built : 01:11:41, Jan 25 2020 NOTICE: sip svc init U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz Reset cause: POR DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial# 06535149 Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Verdin iMX8MM # Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-26clock_imx8mq: Make frac_pll_init() staticPedro Jardim
Since frac_pll_init() is only used in this file, change it to 'static'. This fixes the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:662:5: warning: no previous prototype for ‘frac_pll_init’ [-Wmissing-prototypes] Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
2020-01-26clock_imx8mq: Remove the function sscg_pll_init()Pedro Jardim
Function sscg_pll_init() is not used anywhere, so it can simply be deleted. This was found because of the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:702:5: warning: no previous prototype for ‘sscg_pll_init’ [-Wmissing-prototypes] int sscg_pll_init(u32 pll) ^~~~~~~~~~~~~ Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
2020-01-26clock_imx8mq: Make do_imx8m_showclocks() staticPedro Jardim
Since do_imx8m_showclocks() is only used inside this file, make it 'static'. This fixes the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:836:5: warning: no previous prototype for ‘do_imx8m_showclocks’ [-Wmissing-prototypes] int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
2020-01-26clock_imx8mq: Delete not used init_usb_clk()Pedro Jardim
Function init_usb_clk() is not used anywhere, so it can simply be deleted. This was detected by the following sparse warning: arch/arm/mach-imx/imx8m/clock_imx8mq.c:377:6: warning: no previous prototype for ‘init_usb_clk’ [-Wmissing-prototypes] void init_usb_clk(void) ^~~~~~~~~~~~ Signed-off-by: Pedro Jardim <jardim.c.pedro@gmail.com>
2020-01-20imx8m: clock_imx8mm: Staticize functionsAlifer Moraes
Functions fracpll_configure(), decode_intpll(), decode_fracpll(), get_root_src_clk() and get_root_clk() are used only in the scope of this file, so make them static to fix the following sparse warnings: arch/arm/mach-imx/imx8m/clock_imx8mm.c:50:5: warning: no previous prototype for ‘fracpll_configure’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:271:5: warning: no previous prototype for ‘decode_intpll’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:418:5: warning: no previous prototype for ‘decode_fracpll’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:483:5: warning: no previous prototype for ‘get_root_src_clk’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:527:5: warning: no previous prototype for ‘get_root_clk’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
2020-01-08imx: add i.MX8MP EVK boardPeng Fan
Add basic i.MX8MP EVK board support U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) power_pca9450b_init DDRINFO: start DRAM init DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Failed to find clock node. Check device tree WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) CPU: Freescale i.MX8MP rev1.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MPlus EVK board DRAM: 6 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> mmc list FSL_SDHC: 1 (SD) FSL_SDHC: 2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8m: add imximage-8mp-lpddr4.cfgPeng Fan
Add imximage-8mp-lpddr4.cfg for imximage usage, almost same as i.MX8MN ddr4 cfg, but with different ddr firmware Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8m: only support non-dm code in clock_imx8mm.cPeng Fan
The drivers/clk/imx/*.c are used for CLK dm case, the clock_imx8mm.c is used for non CLK dm case, let's split it. Sometimes it is hard to enable CLK dm in SPL stage, considering code size, malloc size requirement, the splittion will make it easy to use non CLK dm in SPL stage. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8m: add 1GHz fracpll entryPeng Fan
4000MTS DDR needs 1GHz fracpll, so add the entry Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8mp: add basic clockPeng Fan
i.MX8MP has similar architecture as i.MX8MN, but it has different clk root and index, so add that to make i.MX8MP could use the non-dm clock driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8m: add Kconfig entry for i.MX8MPPeng Fan
Add Kconfig entry for i.MX8MP Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx8mp: set BYPASS ID SWAP to avoid AXI bus errorsPeng Fan
Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: get cpu id/type of i.MX8MPPeng Fan
Support get i.MX8MP cpu id and cpu type Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8mq: handle ESDHC in mxc_get_clockPeng Fan
fsl_esdhc_imx driver will call "mxc_get_clock(MXC_ESDHC_CLK + dev->seq)", however mxc_get_clock wrongly handle MXC_ESDHC_CLK as root clk and cause sd card could not be detected in U-Boot proper, as below: "Loading Environment from MMC... unable to select a mode" Handle MXC_ESDHC_CLK in mxc_get_clock to fix the issue. Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Fabio Estevam <festevam@gmail.com>
2019-12-09imx8m: fix rom version check to unbreak some B0 chipsPatrick Wildt
Recently the version check was improved to be able to determine that we're running on SoC revision 2.1. A check for B0 was tightened so that it now must equal 0x20 instead of being bigger than 0x20. On some B0 chips the value returned is 0x1020 instead of 0x20. This means even though it's B0, the check will fail and code relying on the correct chip revision will make wrong decisions. There is no documentation of those bits, but it seems that NXP always uses a byte to encode the revision. Thus remove the upper bits to fix the regression. Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-12-02common: Move some cache and MMU functions out of common.hSimon Glass
These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-05imx: imx8m: fix boot when CONFIG_$(SPL_)CLK not definedPeng Fan
When CONFIG_$(SPL_)CLK not defined, the clock controller device not exist, so to avoid boot failure for platform not have CONFIG_$(SPL_)CLK, add a check. Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx: add i.MX8MN DDR4 board supportPeng Fan
Support pinctrl/clk/sdhc, include ddr4 timing data. Log: U-Boot SPL 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) Normal Boot Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800) CPU: Freescale i.MX8MNano rev1.0 at 24 MHz Reset cause: POR Model: NXP i.MX8MNano DDR4 EVK board DRAM: 2 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx8m: add i.MX8MN ddr4 image cfg filePeng Fan
Add cfg file for i.MX8MN DDR4 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx8mn: add get_boot_devicePeng Fan
No ROM INFO structure on iMX8MN, use new ROM API to get boot device from ROM. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx8mn: set BYPASS ID SWAP to avoid AXI bus errorsPeng Fan
Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx8m: add clk support for i.MX8MNPeng Fan
i.MX8MN has similar architecture with i.MX8MM, so it could reuse the clock code of i.MX8MM, but i.MX8MN has different CCM root configurations, so need a separate root entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx8mn: support get_cpu_revPeng Fan
Add a dummy cpu type and support get_cpu_rev for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05imx: add i.MX8MN kconfig entryPeng Fan
Add i.MX8MN kconfig entry Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03imx: imx8mq: add init_nand_clkPeng Fan
Add init_nand_clk to enable gpmi nand clock. Since i.MX8MQ not use CCF, so we still use legacy mode to configure the clock. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03imx8m: clock: improve irq response latencyPeng Fan
Improve the IRQ response latency by setting GIC root clock source to sys_pll2_200m from osc. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03imx8m: imx8mq: get chip rev for B1 revisionPeng Fan
The i.MX8MQ B1 uses OCOTP_HW_OCOTP_READ_FUSE_DATA register for chip id. It returns a magic number 0xff0055aa. update get_cpu_rev to support it, and enable ocotp clock to access ocotp. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HABStefano Babic
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross architecture purposes. If Secure Boot is required for imx, this means to enable and use the HAB processor in the soc. Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-10-08imx: Add i.MX8MM EVK board support.Peng Fan
Add board and SoC dts Add ddr training code support SD/MMC/GPIO/PINCTRL/UART Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: soc: probe clock device in arch_cpu_init_dmPeng Fan
Because we need to get cpu freq in print_cpuinfo at very early stage, so we need to make sure the ccm be probed. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add clk support for i.MX8MMPeng Fan
Introduce clk implementation for i.MX8MM, including pll configuration, ccm configuration. Mostly will be done clk dm driver, but such as DRAM part, we still use non clk dm driver, because we have limited sram. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: restructure clock.hPeng Fan
i.MX8MQ and i.MX8MM use different analog pll design, but they share same ccm design. Add clock_imx8mq.h for i.MX8MQ keep common part in clock.h Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: rename clock to clock_imx8mqPeng Fan
i.MX8MQ and i.MX8MM has totally different pll design, so rename clock to clock_imx8mq. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: restrict reset_cpuPeng Fan
Make reset_cpu only visible when CONFIG_SYSRESET not defined or CONFIG_SPL_BUILD. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: soc: enable SCTR clock before timer initPeng Fan
To i.MX8MM SCTR clock is disabled by ROM, so before timer init need to enable it. To i.MX8MQ, it does not hurt the clock is enabled again. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: Configure trustzone region 0 for non-secure accessYe Li
Set trustzone region 0 to allow both non-secure and secure access when trust zone is enabled. We found USB controller fails to access DDR if the default region 0 is secure access only. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: set BYPASS ID SWAP to avoid AXI bus errorsPeng Fan
set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: Fix MMU table issue for OPTEE memoryPeng Fan
When running with OPTEE, the MMU table in u-boot does not remove the OPTEE memory from its settings. So ARM speculative prefetch in u-boot may access that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory is set to secure access, then the speculative prefetch will fail and cause various memory issue in u-boot. The fail address register and int_status register in trustzone has logged that speculative access from u-boot. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add get_cpu_rev support for i.MX8MMPeng Fan
There are several variants based on i.MX8MM, add the support in get_cpu_rev Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add IMX8MM kconfig entryPeng Fan
Add IMX8MM kconfig entry Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx: add IMX8MQ kconfig entryPeng Fan
Add IMX8MQ kconfig entry, preparing support IMX8MM Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08imx8m: add image cfg for i.MX8MM lpddr4Peng Fan
There is no HDMI on i.MX8MM, so we need to remove HDMI entry, then we could not reuse imximage.cfg, so create a new one. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25imx: i.MX8MQ: clear ocotp error bitPeng Fan
In case ocotp error bit is set, clear it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-09imx8m: clock: Fix oscillator valuesFabio Estevam
OSC_27M_CLK should return 27MHz and OSC_32K_CLK should return 32768Hz to reflect the reality. This also keeps the values in sync with the Linux clock tree. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-01-01imx: add i.MX8MQ EVK supportPeng Fan
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM. The boot log with Arm trusted firmware console enabled: " U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) PMIC: PFUZE100 ID=0x10 Normal Boot Trying to boot from MMC2 NOTICE: Configureing TZASC380 NOTICE: BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty NOTICE: BL31: Built : 09:28:54, Nov 8 2018 lpddr4 swffc start NOTICE: sip svc init U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz Reset cause: POR Model: Freescale i.MX8MQ EVK DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 using MAC address from ROM eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 " Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2019-01-01imx: imx8m: introduce imximage cfg filePeng Fan
imximage.cfg will be used to generate the flash.bin Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: imx8m: clock refactor dram pll partPeng Fan
Refactor dram_pll_init to accept args to configure different pll freq. Introduce dram_enable_bypass and dram_disable_bypass Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01imx: rename mx8m,MX8M to imx8m,IMX8MPeng Fan
Rename mx8m,MX8M to imx8m,IMX8M Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jon Nettleton <jon@solid-run.com>
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