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2018-09-14pico-imx6ul: Convert to SPLFabio Estevam
There are two versions of imx6ul pico SOMs: one with 256MB and another one with 512MB of RAM. Convert to SPL so that both versions can be supported. This patch doesn't rework the clock initialization to avoid changing the behavior in this same patch, so it will be cleaned up in future. Currently only the 256MB is tested/supported. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2018-09-04imx: mx7: add system suspend/resume supportAnson Huang
This patch adds system suspend/resume support, when linux kernel enters deep sleep mode, SoC will go into below mode: - CA7 platform goes into STOP mode; - SoC goes into DSM mode; - DDR goes into self-refresh mode; - CPU0/SCU will be powered down. When wake up event arrives: - SoC DSM mdoe exits; - CA7 platform exit STOP mode, SCU/CPU0 power up; - Invalidate L1 cache; - DDR exit self-refresh mode; - Do secure monitor mode related initialization; - Jump to linux kernel resume entry. Belwo is the log of 1 iteration of system suspend/resume: [ 338.824862] PM: suspend entry (deep) [ 338.828853] PM: Syncing filesystems ... done. [ 338.834433] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 338.842939] OOM killer disabled. [ 338.846182] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 338.869717] PM: suspend devices took 0.010 seconds [ 338.877846] Disabling non-boot CPUs ... [ 338.960301] Retrying again to check for CPU kill [ 338.964953] CPU1 killed. [ 338.968104] Enabling non-boot CPUs ... [ 338.973598] CPU1 is up [ 339.267155] mmc1: queuing unknown CIS tuple 0x80 (2 bytes) [ 339.275833] mmc1: queuing unknown CIS tuple 0x80 (7 bytes) [ 339.284158] mmc1: queuing unknown CIS tuple 0x80 (6 bytes) [ 339.385065] PM: resume devices took 0.400 seconds [ 339.389836] OOM killer enabled. [ 339.392986] Restarting tasks ... done. [ 339.398990] PM: suspend exit The resume entry function has to initialize stack pointer before calling C code, otherwise there will be an external abort occur, in additional, invalidate L1 cache must be done in secure section as well, so this patch also adds assembly code back and keep it as simple as possible. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Tested-by: Stefan Agner <stefan@agner.ch>
2018-09-04imx: mx7: add gpc initialization for low power modeAnson Huang
Add i.MX7D GPC initialization for low power mode support like system suspend/resume from linux kernel: - Pending IOMUXC IRQ to workaround GPC state machine issue; - Mask all GPC interrupts for M4/C0/C1; - Configure SCU timing; - Configure time slot ack; - Configure C0/C1 power up/down timing; - Configure wakeup source mechanism; - Disable DSM/RBC related settings. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-04imx: mx7: psci: improve cpu hotplug flowAnson Huang
This patch improves cpu hotplug, previous cpu_off implementation is NOT safe, a CPU can NOT power down itself in runtime, it will cause system bus hang due to pending transaction. So need to use other online CPU to kill it when it is ready for killed. Here use SRC parameter register and a magic number of ~0 as handshake for killing a offline CPU, when the online CPU checks the psci_affinity_info, it will help kill the offline CPU according to the magic number stored in SRC parameter register. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-31dm: Fix CMD_DM enablingMichal Simek
The patch "dm: Change CMD_DM enabling" (sha1: 08a00cba06a7e608ae65e3d7ea225cf8c639429d) was incorrectly updated and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice. This patch is fixing it. Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-30Kconfig: Sort bool, default, select and imply optionsMichal Simek
Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30dm: Change CMD_DM enablingMichal Simek
CMD_DM is used for debug purpose and it shouldn't be enabled by default via Kconfig. Unfortunately this is in the tree for quite a long time that's why solution is to use imply DM for all targets which are enabling DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30Kconfig: Sort bool, default, select and imply optionsMichal Simek
Fix Kconfig bool, default, select and imply options to be alphabetically sorted. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-07-30Kconfig: Replace spaces with tabs and missing newlineMichal Simek
Trivial Kconfig cleanup. Use tabs instead of spaces and every Kconfig entry should be separated by newline. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-23imx: i.mx6q: imx6q_logic: Migrate to SPL and enable SDPAdam Ford
Since the vast majority of i.MX6 boards are migrating to SPL, this patch converts im6q_logic to SPL and enables the SDP for loading SPL and u-boot.img over USB. The Falcon mode only supports NAND flash as of now due to limited space/RAM, but all i.MX6D/Q SOM's from Logic PD have internal NAND from which to boot. Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23pico-imx7d: Add SPL supportFabio Estevam
Convert pico-imx7d to SPL support. There are two variants of pico-imx7d SOMs: - One with 512MB of RAM - One with 1GB of RAM The 512MB module contains two Hynix H5TC2G63GFR-PBA. The 1GB module contains two Hynix H5TC4G63GFR-PBA. The RAM size is determined in runtime by reading GPIO1_12. While at it, also add USB Serial Download mode support as it is very helpful for loading SPL and u-boot.img via imx_usb_loader. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2018-07-23imx: mx7: psci: implement MIGRATE_INFO_TYPEStefan Agner
Implement MIGRATE_INFO_TYPE. This informs Linux that no migration for the trusted operating system is necessary: [ 0.000000] psci: Trusted OS migration not required Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23imx: mx7: psci: support CPU0 on/offStefan Agner
So far psci_cpu_(on|off) only worked for CPU1. Allow to control CPU0 too. This allows to run the Linux PSCI checker successfully: [ 2.213447] psci_checker: PSCI checker started using 2 CPUs [ 2.219107] psci_checker: Starting hotplug tests [ 2.223859] psci_checker: Trying to turn off and on again all CPUs [ 2.267191] IRQ21 no longer affine to CPU0 [ 2.293266] Retrying again to check for CPU kill [ 2.302269] CPU0 killed. [ 2.311648] psci_checker: Trying to turn off and on again group 0 (CPUs 0-1) [ 2.354354] IRQ21 no longer affine to CPU0 [ 2.383222] Retrying again to check for CPU kill [ 2.392148] CPU0 killed. [ 2.398063] psci_checker: Hotplug tests passed OK [ 2.402910] psci_checker: Starting suspend tests (10 cycles per state) [ 2.410019] psci_checker: cpuidle not available on CPU 0, ignoring [ 2.416452] psci_checker: cpuidle not available on CPU 1, ignoring [ 2.422757] psci_checker: Could not start suspend tests on any CPU [ 2.429370] psci_checker: PSCI checker completed Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23imx: mx7: psci: provide complete PSCI 1.0 implementationStefan Agner
PSCI 1.0 require PSCI_VERSION, PSCI_FEATURES, AFFINITY_INFO and CPU_SUSPEND to be implemented. Commit 0ec3d98f7692 ("mx7_common: use psci 1.0 instead of 0.1") marked the i.MX 7 implementation to be PSCI 1.0 compliant but failed to implement those functions. Especially the missing PSCI version callback was noticeable when booting Linux: [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv65535.65535 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.0 This patch provides a minimal implementation thereof. With this patch applied Linux detects PSCI 1.0: [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.0 Fixes: 0ec3d98f7692 ("mx7_common: use psci 1.0 instead of 0.1") Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23imx: mx7: psci: use C code exclusivelyStefan Agner
There is no need for assembly in the platform specific part of the PSCI implementation. Note that this does not make it a complete PSCI 1.0 implementation yet but aids to do so in upcoming patches. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23imx: imx6: Add comment to gpr_init functionMichael Trimarchi
This function can be used only for some of the nxp SoC. Make it explicit in the comment. This adjust a bit commit 3aa4b703b483f165dd ("imx: imx6: Move gpr_init() function to soc.c") Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-23mx7: Remove BMODE supportFabio Estevam
i.MX7 does not support BMODE due to the erratum e10574 ("Watchdog: A watchdog timeout or software trigger will not reset the SOC"), so remove its support. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-07-23imx: mx6: Fix implementantion reset_miscMichael Trimarchi
lcdif_power_down should not be included in spl build to avoid build failure introduced by commit eb111bb31d882877e75e6b8083808dcaf6493b92 Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-07-23board: toradex: add Colibri iMX6ULL supportStefan Agner
Add support for the Colibri iMX6ULL module which comes with on-board raw NAND. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-19env: common: accept flags on reset to default envYaniv Levinsky
The function set_default_env() sets the hashtable flags for import_r(). Formally set_default_env() doesn't accept flags from its callers. In practice the caller can (un)set the H_INTERACTIVE flag, but it has to be done using the first character of the function's string argument. Other flags like H_FORCE can't be set by the caller. Change the function to accept flags argument. The benefits are: 1. The caller will have to explicitly set the H_INTERACTIVE flag, instead of un-setting it using a special char in a string. 2. Add the ability to propagate flags from the caller to himport(), especially the H_FORCE flag from do_env_default() in nvedit.c that currently gets ignored for "env default -a -f" commands. 3. Flags and messages will not be coupled together. A caller will be able to set flags without passing a string and vice versa. Please note: The propagation of H_FORCE from do_env_default() does not introduce any functional changes, because currently himport_r() is set to destroy the old environment regardless if H_FORCE flag is set or not. More changes are needed to utilize the propagation of H_FORCE. Signed-off-by: Yaniv Levinsky <yaniv.levinsky@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2018-07-02board/aries: RemoveTom Rini
The various Aries Embedded boards have been orphaned for a year and no one has come forward to take care of them. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-06-30mx5: Select ARM_CORTEX_A8_CVE_2017_5715Fabio Estevam
On a 4.18-rc1 kernel the following warning is seen on i.MX51 and i.MX53: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable Select the ARM_CORTEX_A8_CVE_2017_5715 workaround for i.MX51/i.MX53 to fix the problem. With this patch applied the kernel reports: CPU0: Spectre v2: using BPIALL workaround Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-06-27Merge git://git.denx.de/u-boot-imxTom Rini
2018-06-19common: Fix cpu nr type which is always unsigned typeMichal Simek
cpu_cmd() is reading cpu number via simple_strtoul() which is always unsigned type. Platform code implementations are not expecting that nr can be negative and there is not checking in the code for that too. This patch is using u32 type for cpu number to make sure that platform code get proper value range. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-18imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platformsYe Li
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed". ROM sets this bit in normal boot flow, but when in serial download mode, it is not set. Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com> [fabio: adapted to U-Boot mainline codebase and make checkpatch happy] Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-05-18arm: imx53: Add support for imx53 boards from K+PLukasz Majewski
This commit adds support for DDC and HSC boards from K+P in u-boot. Console output: U-Boot 2018.05-rc2-00090-g752b7ed6f9 (Apr 26 2018 - 14:24:24 +0200) CPU: Freescale i.MX53 rev2.1 at 800 MHz Reset cause: WDOG Model: K+P iMX53 DRAM: 512 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... OK In: serial Out: serial Err: serial Module EEPROM: ID: TQMa53-CB.0401 SN: 63152762 MAC: 00:0b:64:03:14:2a BBoard:40x0 Rev:10 Net: eth0: ethernet@63fec000 Hit any key to stop autoboot: 0 Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-05-18i.MX6DL: mamoj: Add PFUZE100 supportJagan Teki
MX6DL Mamoj boards has Freescale PFUZE100 PMIC, add support for it through DM_PMIC dt definition. pmic log: Reviewed-by: Stefano Babic <sbabic@denx.de> ======== => pmic list | Name | Parent name | Parent uclass @ seq | pfuze100@08 | i2c@021f8000 | i2c @ 3 => pmic dev pfuze100@08 dev: 0 @ pfuze100@08 => pmic dump Dump pmic: pfuze100@08 registers 0x00: 10 00 00 21 00 01 3f 01 00 7f 00 00 00 00 00 81 0x10: 00 00 3f 00 00 00 00 00 00 00 00 10 00 00 00 00 0x20: 2b 2b 2b 08 c4 00 00 00 00 00 00 00 00 00 2b 2b 0x30: 2b 08 c4 00 00 72 72 72 08 d4 00 00 2c 2c 2c 08 0x40: e4 00 00 2c 2c 2c 08 e4 00 00 6f 6f 6f 08 f4 00 0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x60: 00 00 00 00 00 00 48 00 00 00 10 06 1e 1e 17 10 0x70: 1a 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Simone CIANNI <simone.cianni@bticino.it> Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
2018-05-18i.MX6DL: mamoj: Add I2C supportJagan Teki
i.MX6DL Mamoj has i2c3 and i2c4 buses, add support through DM_I2C with dt definition. i2c log: Reviewed-by: Stefano Babic <sbabic@denx.de> ======= => i2c bus Bus 2: i2c@021a8000 Bus 3: i2c@021f8000 => i2c dev 2 Setting bus to 2 => i2c speed 400000 Setting bus speed to 400000 Hz => i2c probe Valid chip addresses: 20 51 53 => i2c md 53 0xff 00ff: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ => i2c md 51 0xff 00ff: a8 08 40 50 09 43 46 52 42 18 80 8e ae a9 d0 53 ..@P.CFRB......S => i2c dev 3 Setting bus to 3 => i2c speed 100000 Setting bus speed to 100000 Hz => i2c probe Valid chip addresses: 08 40 48 4B => i2c md 08 0xff 00ff: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Simone CIANNI <simone.cianni@bticino.it> Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
2018-05-18i.MX6: board: Add BTicino i.MX6DL Mamoj initial supportJagan Teki
Add initial support for i.MX6DL BTicino Mamoj board. Mamoh board added: - SPL - SPL_DM - SPL_OF_CONTROL - DM for U-Boot proper - OF_CONTROL for U-Boot proper - eMMC - FEC - Boot from eMMC - Boot from USB SDP Signed-off-by: Simone CIANNI <simone.cianni@bticino.it> Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-05-17mx6: Select CONFIG_MP with MX6_SMPPeter Robinson
It makes sense to select the MP multi processor option at the same time we select the other SMP options needed for SMP capable i.MX6 SoCs. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2018-05-17mx31: Convert MX31_HCLK_FREQ and MX31_CLK32 to Kconfig.Magnus Lilja
Also remove the #ifdef's from clock.h since the Kconfig values defaults the to old default values in clock.h. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-17mx31pdk: Convert CONFIG_MX31 flag to use Kconfig.Magnus Lilja
Move CONFIG_MX31 from mx31pdk.h to mx31pdk_defconfig and introduce necessary Kconfig changes as well. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-17board: ge: bx50v3: remove redundant targetsIan Ray
This replaces TARGET_GE_B{4,6,8}50V3 with common TARGET_GE_BX50V3. The boards are identified automatically at runtime. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
2018-05-07imx7: psci: save context id in cpu_on commandPatrick Delaunay
Replace the psci_save_target_pc call by the new function psci_save(cpu, pc,context_id) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-30Merge git://git.denx.de/u-boot-imxTom Rini
2018-04-28arm: move SYS_ARCH_TIMER to KConfigAndre Przywara
SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch timer) in U-Boot. At the moment it is mandatory for ARMv8 and used by a few ARMv7 boards. Add a proper Kconfig symbol to express this dependency properly, allowing certain board configuration to later disable arch timer in case there are any problems with it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [tuomas: rebase + fix conflicts and resync with moveconfig & use select] Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-26imx6ul: opos6ul: in Serial Downloader boot mode use ymodemSébastien Szymanski
When booting in Serial Downloader mode load the U-Boot image using ymodem. Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2018-04-26imx6ul: opos6ul: add SPL_DM supportSébastien Szymanski
Since commit commit 152038ea1886 ("i.MX6UL: icore: Add SPL_OF_CONTROL support") the OPOS6UL board doesn't boot anymore. Adding SPL_DM support makes the board boot again. Fixes: commit 152038ea1886 ("i.MX6UL: icore: Add SPL_OF_CONTROL support") Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2018-04-15Merge git://git.denx.de/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-15imx: Create distinct pre-processed mkimage config filesTrent Piepho
Each imx image is created by a separate sub-make and during this process the mkimage config file is run though cpp. The cpp output is to the same file no matter what imx image is being created. This means if two imx images are generated in parallel they will attempt to independently produce the same pre-processed mkimage config file at the same time. Avoid the problem by making the pre-processed config file name unique based on the imx image it will be used in. This way each image will create a unique config file and they won't clobber each other when run in parallel. This should fixed the build bug referenced in b5b0e4e3 ("imximage: Remove failure when no IVT offset is found"). Cc: Breno Lima <breno.lima@nxp.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-15imx: mx7: snvs: Add an SNVS init routineBryan O'Donoghue
Working with HAB on the i.MX7 we've encountered a case where a board that successfully authenticates u-boot when booting Linux via OPTEE subsequently fails to properly bring up the RTC. The RTC registers live in the low-power block of the Secure Non-Volatile Storage (SNVS) block. The root cause of the error has been traced to the HAB handing off the SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the Non-Privileged Software Access Enable bit is zero. In ordinary circumstances this is OK since we typically do not run in TZ mode, however when we boot via HAB and enablng TrustZone, it is required to set HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have sufficient permissions to manipulate the SNVS-LP block. On our reference board it is the difference between Linux doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered 30370000.snvs:snvs-rtc-lp as rtc0 snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864) and doing this: root@imx7s-warp-mbl:~# dmesg | grep rtc snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034 snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038 snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000 snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004 snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110 snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110 hctosys: unable to open rtc device (rtc0) Note bit 1 of LPCR is not set in the second case and is set in the first case and that bit 31 of HPCOMR is set in the second case but not in the first. Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone and continue onto the kernel. The kernel then has the necessary permissions to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in contrast - in the failing case the non-privileged kernel cannot do so. This patch adds a simple init_snvs() call which sets the permission-bit called from soc.c for the i.MX7. It may be possible, safe and desirable to perform this on other i.MX processors but for now this is only tested on i.MX7 as working. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-04-15imx: board: Add support for the K+P's kp_imx6q_tpc boardLukasz Majewski
This commit provides support for Kieback & Peter GmbH IMX6Q based TPC board. U-boot console output: U-Boot SPL 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) Trying to boot from MMC1 U-Boot 2018.05-rc1-00005-g631e2d01fd (Apr 04 2018 - 21:16:24 +0200) CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 37C Reset cause: POR Board: K+P KP_IMX6Q_TPC i.MX6Q Watchdog enabled I2C: ready DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: FEC [PRIME] Autoboot in 3 seconds
2018-04-15imx: hab: Provide hab_auth_img_or_fail commandBryan O'Donoghue
This patch adds hab_auth_img_or_fail() a command line function that encapsulates a common usage of authenticate and failover, namely if authenticate image fails, then drop to BootROM USB recovery mode. For secure-boot systems, this type of locked down behavior is important to ensure no unsigned images can be run. It's possible to script this logic but, when done over and over again the environment starts get very complex and repetitive, reducing that script repetition down to a command line function makes sense. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Breno Lima <breno.lima@nxp.com>
2018-04-15imx: mx7: Add comment to describe OTP TESTER registersBryan O'Donoghue
The tester registers provide a unique chip-level identifier which get_board_serial() returns in a "struct tag_serialnr". This patch documents the properties of the registers; in summary. 31:0 OCOTP_TESTER0 (most significant) - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID OCOTP_TESTER1 (least significant) 31:24 - The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 23:16 - The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID 15:11 - The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID 10:0 - FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID The 64 bits of data generate a unique serial number per-chip. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-15imx: mx7: Fix CONFIG_SERIAL_TAG compilationBryan O'Donoghue
Currently when we define CONFIG_SERIAL_TAG we will barf with a failure to define "struct tag_serialnr". This structure is defined in <asm/setup.h>, this patch includes <asm/setup.h> to fix. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-15ARM: mx6: ddr: Add write leveling correction codeMarek Vasut
When the DDR calibration is enabled, a situation may happen that it will fail on a few select boards out of a whole production lot. In particular, after the first write leveling stage, the MPWLDECTRLx registers will contain a value 0x1nn , for nn usually being 0x7f or slightly lower. What this means is that the HW write leveling detected that the DQS rising edge on one or more bundles arrives slightly _after_ CLK and therefore when the DDR DRAM samples CLK on the DQS rising edge, the CLK signal is already high (cfr. AN4467 rev2 Figure 7 on page 18). The HW write leveling then ends up adding almost an entire cycle (thus the 0x17f) to the DQS delay, which indeed aligns it, but also triggers subsequent calibration failure in DQS gating due to this massive offset. There are two observations here: - If the MPWLDECTRLx value is corrected from 0x17f to 0x0 , then the DQS gating passes, the entire calibration passes as well and the DRAM is perfectly stable even under massive load. - When using the NXP DRAM calibrator for iMX6/7, the value 0x17f or so in MPWLDECTRx register is not there, but it is replaced by 0x0 as one would expect. Someone from NXP finally explains why, quoting [1]: " Having said all that, the DDR Stress Test does something that we do not advertise to the users. The Stress Test iself looks at the values of the MPWLDECTRL0/1 fields before reporting results, and if it sees any filed with a value greater than 200/256 delay (reported as half-cycle = 0x1 and ABS_OFFSET > 0x48), the DDR Stress test will reset the Write Leveling delay for this lane to 0x000 and not report it in the log. The reason that the DDR Stress test does this is because a delay of more than 78% a clock cycle means that the DQS edge is arriving within the JEDEC tolerence of 25% of the clock edge. In most cases, DQS is arriving < 5% tCK of the SDCLK edge in the early case, and it does not make sense to delay the DQS strobe almost a full clock cycle and add extra latency to each Write burst just to make the two edges align exactly. In this case, we are guilty of making a decision for the customer without telling them we are doing it so that we don't have to provide the above explanation to every customer. They don't need to know it. " This patch adds the correction described above, that is if the MPWLDECTRx value is over 0x148, the value is corrected back to 0x0. [1] https://community.nxp.com/thread/456246 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-03-29imx7: spl: Check for Serial Downloader in spl_boot_deviceEran Matityahu
Similarly to imx6, before reading the boot device, first check bmode to see if the serial downloader has been selected explicitly, then check whether the serial downloader has been activated due to unbootable primary boot devices (e.g. empty eMMC). If the serial downloader is activated, return BOOT_DEVICE_BOARD. This allows SPL with SDP support to wait for the U-Boot image to be loaded via the serial download protocol using imx_usb_loader. Signed-off-by: Eran Matityahu <eran.m@variscite.com>
2018-03-13imx: hab: Convert DCD non-NULL error to warningBryan O'Donoghue
commit 8c4037a09a5c ("imx: hab: Ensure the IVT DCD pointer is Null prior to calling HAB authenticate function.") makes the DCD field being NULL a dependency. This change though will break loading and executing of existing pre-signed binaries on a u-boot update i.e. if this change is deployed on a board you will be forced to redo all images on that board to NULL out the DCD. There is no prior guidance from NXP that the DCD must be NULL similarly public guidance on usage of the HAB doesn't call out this NULL dependency (see boundary devices link). Since later SoCs will reject a non-NULL DCD there's no reason to make a NULL DCD a requirement, however if there is an actual dependency for later SoCs the appropriate fix would be to do SoC version checking. Earlier SoCs are capable (and happy) to authenticate images with non-NULL DCDs, we should not be forcing this change on downstream users - particularly if it means those users now must rewrite their build systems and/or redeploy signed images in the field. Fixes: 8c4037a09a5c ("imx: hab: Ensure the IVT DCD pointer is Null prior to calling HAB authenticate function.") Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com> Cc: Breno Lima <breno.lima@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Link: https://boundarydevices.com/high-assurance-boot-hab-dummies Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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