uboot-2021-rebase.git - uboot 2021 rebase, to fix booting on modern SD cards, from https://github.com/fifteenhex/u-boot/tree/am335x_som

Age	Commit message (Collapse)	Author
2020-05-18	common: Drop linux/bitops.h from common header	Simon Glass
	Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-08	arm64: versal: Define board_late_init for versal	Siva Durga Prasad Paladugu
	Define board_late_init which performs bootmode detection and prepares corresponding distro boot commaand sequence. Also disable it for mini platforms because simply there is no need to have it enabled. But also disable it for virtual platform because Qemu is not modelling this register space that's why travis testing would fail. This configuration should be reverted when mainline Qemu is updated. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14	arm64: versal: Add new Kconfig SYS_MEM_RSVD_FOR_MMU	Siva Durga Prasad Paladugu
	This patch adds new config option which is used for reserving a specific memory for MMU Table and in this case we are using TCM for that purpose. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16	arm64: versal: Add support for new Xilinx Versal ACAPs	Michal Simek
	Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>