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2015-08-02imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6ULPeng Fan
Since i.MX6UL's cache line size is 64bytes, need to define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02imx: mx6ul: Update imx registers head filePeng Fan
1. Update imx register base address for i.MX6UL. 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE. 3. Remove #ifdef for register addresses that equal to "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips. 4. According fuse map, complete fuse_bank4_regs. 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX, because we can use runtime check Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02imx: mx6ul: Add pins IOMUX head filePeng Fan
Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
2015-08-02imx: mx6ul: Add i.MX6UL CPU typePeng Fan
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which is not real id from DIGPROG register, so change i.MX6D to value 0x67 which was not occupied. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
2015-08-02arm: mx6: kconfig: don't select CPU_V7 per boardNikita Kiryanov
CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again by boards that depend on ARCH_MX6. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2015-08-02arm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6Nikita Kiryanov
cm-fx6 is an MX6 based board, and the menuconfig hierarchy should reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2015-08-02imx: mx6qp Enable PRG clock for IPUPeng Fan
The i.MX6DQP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li
Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02imx: mx6: ccm: Change the clock settings for i.MX6QPPeng Fan
Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. In c files, use runtime check and discard #ifdef. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02imx: add cpu type for i.MX6QP/DPPeng Fan
Add cpu type for i.MX6QP/DP. This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2015-07-31armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu
Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-07-29Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2015-07-28T210: Add support for 64-bit T210-based P2571 boardTom Warren
Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-07-28P2571: dts: Add DT file for Tegra210 P2571 boardTom Warren
Based on T124 Venice2. SDMMC1 is SD-card slot. Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-07-28ARM: Tegra210: Add support to common Tegra source/config filesTom Warren
Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28ARM: Tegra210: Add SoC code/include files for T210Tom Warren
All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-07-28Tegra: Rework KConfig options to allow 64-bit builds (T210)Tom Warren
Moved Tegra config options to mach-tegra/Kconfig so that both 32-bit and 64-bit builds can co-exist for Tegra SoCs. T210 will be 64-bit only (no SPL) and will require a 32-bit AVP/BPMP loader. Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-07-28Tegra210: Fix 64-bit build warning about save_boot_params_ret()Tom Warren
Simon's 'tegra124: Implement spl_was_boot_source()' needs a prototype for save_boot_params_ret() to build cleanly for 64-bit Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-07-28ARM: tegra: Initialize timer earlierThierry Reding
A subsequent patch will enable the use of the architected timer on ARMv8. Doing so implies that udelay() will be backed by this timer implementation, and hence the architected timer must be ready when udelay() is first called. The first time udelay() is used is while resetting the debug UART, which happens very early. Make sure that arch_timer_init() is called before that. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-07-28ARM: tegra: Use standard cache enable for 64-bitThierry Reding
On 64-bit SoCs the I-cache isn't enabled in early code, so the default cache enable functions for 64-bit ARM can be used. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCsThierry Reding
Most peripherals on Tegra can do DMA only to the lower 32-bit address space, even on 64-bit SoCs. This limitation is typically overcome by the use of an IOMMU. Since the IOMMU is not entirely trivial to set up and serves no other purpose (I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to the lower 32-bit address space for RAM. This ensures that the physical addresses of buffers that are programmed into the various DMA engines are valid and don't alias to lower addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28armv8/cache: Fix page table creationThierry Reding
While generating the page tables, a running integer index is shifted by SECTION_SHIFT (29) and causes overflow for any integer bigger than 7. The page tables therefore alias to the same 8 sections and cause U-Boot to hang once the MMU is enabled. Fix this by making the index a 64-bit unsigned integer and so avoid the overflow. swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and "j" varies depending on RAM size; from 4 to 11 for a board with 4GB at physical address 2GB, as some Tegra boards have. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-07-28Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini
2015-07-28ARM: zynqmp: Wire up SATA for the boardMichal Simek
Enable SATA for the ZynqMP targets. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynqmp: Wire up ethernet controllersMichal Simek
Wire up ethernet controllers and enable MII and BOOTP options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: Add support for zc770-xm011Michal Simek
Add xm011 DTS file and related configs and configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Update zc770 dtsesMichal Simek
Platform DTSes are missing content needed for platform to be able to use OF binding and DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keysMichal Simek
Adds the two MIO connected pushbuttons on the zc702 board to the devicetree as a single multi-key device for us with the gpio-keys driver. Signed-off-by: Ezra Savard <ezra.savard@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add missing interrupt for L2 pl310Michal Simek
Add pl310 interrupt to the Zynq devicetree. Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Get rid of ps-clk-frequencyMichal Simek
ps-clk-frequency is platform specific setting and shouldn't be the part of DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Update years in copyrightMichal Simek
Trivial. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernelMichal Simek
Syncup with the latest DT from the Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add reference to bus nodeMichal Simek
For adding OCM memory in platform DTS is necessary to have reference to amba bus. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add pinctrl nodeMichal Simek
Add pinctrl node to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Cleanup address-cells and size-cellsMichal Simek
Remove unneeded address-cells form intc node because it is already setup in parent node. Add missing address-cells and size-cells to eth node to be shared for every platform DTSes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Clean up timer device tree nodesMichal Simek
Separate IRQ cells from each other for easier reading. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Use the zynq binding with macbMichal Simek
Use the new zynq binding for macb ethernet, since it will disable half duplex gigabit like the Zynq TRM says to do. Also allow the compatible cadence gem binding that won't disable half duplex but works otherwise. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Fix GEM register area sizeMichal Simek
The size of the GEM's register area is only 0x1000 bytes. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28spi: Fix zynq SPI bindingMichal Simek
Zynq is using Cadence IP where binding is documented in the Linux kernel and there is no reason to use different binding. Synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Remove 222 MHz OPPMichal Simek
Due to dependencies between timer and CPU frequency, only changes by powers of two are allowed. The clocksource driver prevents other changes, but with cpufreq and its governors it can result in being spammed with error messages constantly. Hence, remove the 222 MHz OPP. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Migrate UART to Cadence bindingMichal Simek
The Zynq UART is Cadence IP and the driver has been renamed accordingly. Migrate the DT to use the new binding for the UART driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add a fixed regulator for CPU voltageMichal Simek
To silence the warning cpufreq_cpu0: failed to get cpu0 regulator: -19 from the cpufreq driver regarding a missing regulator, add a fixed regulator to the DT. Zynq does not support voltage scaling and the CPU rail should always be supplied with 1 V, hence it is added in the SOC-level dtsi. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add missing nodes to DTSIMichal Simek
Add ADC, CAN, GPIO, MC, DMA, DEVCFG, USB, Watchdog IPs to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Use the right names for nodesMichal Simek
Based on SPEC you right names with addresses. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28zynqmp: Add support for IP detection via SLCRMichal Simek
SLCR can be used for IP configuration setting. Add SLCR skeleton to enable run time checking. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28zynqmp: mp: Simplify set_r5_start handlingMichal Simek
Pass directly boot_addr which is LOVEC (0) or HIVEC (0xffff0000). No reason to use magic values 0 and 1. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28zynqmp: Define ep config for ZynqMPSiva Durga Prasad Paladugu
Define a new config "zynqmp_ep" for ZynqMP instead of xilinx_zynqmp. This defconfig supports all emulation platforms of ZynqMP. Also renamed TARGET_XILINX_ZYNQMP to ARCH_ZYNQMP. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28zynqmp: Kconfig: Move zynqmp KconfigSiva Durga Prasad Paladugu
Move the zynqmp Kconfig from board to arch as there may be different boards under same architecture. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-27arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN valuesThierry Reding
The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN can only accept certain values, and the set of acceptable values differs between the AArch32 and AArch64 instructions sets. The default value of CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0 assembly so it can handle completely arbitrary values. Signed-off-by: Thierry Reding <treding@nvidia.com> [twarren: trimmed Thierry's patch to remove changes already present] Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, cleaned up patch, wrote description, re-wrote subject] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-07-27ARM: tegra: Build warning fixes for 64-bitThierry Reding
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, stripped out changes not strictly related to warnings] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-01-02 16:35:39 +0000