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2020-01-08imx: imx8mp: add basic clockPeng Fan
i.MX8MP has similar architecture as i.MX8MN, but it has different clk root and index, so add that to make i.MX8MP could use the non-dm clock driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08arm: dts: add i.MX8MP pinfunc headerPeng Fan
Add i.MX8MP pinfunc header for dts usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: spl: support i.MX8MP spl_boot_devicePeng Fan
i.MX8MP follows i.MX8MN, so just let it use spl_board_boot_device Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8m: add Kconfig entry for i.MX8MPPeng Fan
Add Kconfig entry for i.MX8MP Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: cpu: enlarge bit mask to 0x1FF for cpu typePeng Fan
i.MX8MP use 0x182 as dummy id, 0xFF is not able the get the highest bit, so enlarge bit mask to 0x1FF to make it could detect cpu type correctly Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx8mp: set BYPASS ID SWAP to avoid AXI bus errorsPeng Fan
Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: get cpu id/type of i.MX8MPPeng Fan
Support get i.MX8MP cpu id and cpu type Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08imx: imx8mq: handle ESDHC in mxc_get_clockPeng Fan
fsl_esdhc_imx driver will call "mxc_get_clock(MXC_ESDHC_CLK + dev->seq)", however mxc_get_clock wrongly handle MXC_ESDHC_CLK as root clk and cause sd card could not be detected in U-Boot proper, as below: "Loading Environment from MMC... unable to select a mode" Handle MXC_ESDHC_CLK in mxc_get_clock to fix the issue. Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Fabio Estevam <festevam@gmail.com>
2020-01-07stm32mp1: reset coprocessor status at cold bootFabien Dessenne
Reset ResourceTableAddress and CoprocessorState at cold boot, preserve these values at standby wakeup. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07stm32mp1: declare backup registers for coprocessorFabien Dessenne
Use the backup register #17 as coprocessor resource table address and backup register #18 as coprocessor state. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07board: amlogic: select PWRSEQ for all amlogic platformAnand Moon
commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc") introduce CONFIG_PWRSEQ for power sequence for eMMC module on amlogic platform, so enable this to all amlogic boards. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-01-07Merge tag 'u-boot-imx-20200107' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
2020-01-07Merge tag 'u-boot-atmel-2020.04-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2020.04 cycle This feature set is a patch series from Tudor Ambarus which includes parsing of the spi flash SFDP parser for SST flashes, and using those tables to retrieve unique saved per device MAC address. This is then used as base mac address on the SAMA5D2 Wireless SOM EK board.
2020-01-07arm: socfpga: stratix10: Enable SMMU accessThor Thayer
Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07arm: socfpga: agilex: Enable Agilex SoC buildLey Foon Tan
Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: dts: agilex: Add base dtsi and devkit dtsLey Foon Tan
Add device tree files for Agilex SoC platform. socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains Uboot specific DT properties. socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux (kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add SPL for Agilex SoCLey Foon Tan
Add SPL support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: agilex: Add clock handoff offset for AgilexLey Foon Tan
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add clock wrapper functionsLey Foon Tan
Add clock wrapper functions call to clock DM functions to get clock frequency and used in cm_print_clock_quick_summary(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07clk: agilex: Add clock driver for AgilexLey Foon Tan
Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHzLey Foon Tan
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz. Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex clock manager common codeLey Foon Tan
Move Stratix10 and Agilex clock manager common code to new header file. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add system manager supportLey Foon Tan
Add system manager support for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan
Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add reset manager supportLey Foon Tan
Add reset manager support for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex reset manager common codeLey Foon Tan
Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*. Remove unused RSTMGR_XXX defines. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move firewall code to firewall fileLey Foon Tan
Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add base address for Intel Agilex SoCLey Foon Tan
Add base address for Intel Agilex SoC. Reuse base_addr_s10.h for Agilex, only one base address is different from S10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert clock manager from struct to definesLey Foon Tan
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert system manager from struct to definesLey Foon Tan
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert reset manager from struct to definesLey Foon Tan
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodesLey Foon Tan
Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL. In preparation to get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07ARM: dts: Import Khadas VIM3L DT from Linux 5.5-rc1Christian Hewitt
Import the Khadas VIM3L device-tree from [1] [1] e42617b825f8 ("Linux 5.5-rc1") Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-01-07ARM: mxs: spl_boot.c: make early_delay more robustRasmus Villemoes
It's true that booting normally doesn't take long enough for the register to roll (which actually happens in a little over an hour, not just a few seconds). However, the counter starts at power-on, and if the board is held in reset to be booted over USB, one actually risks hitting wrap-around during boot, which can both result in too short delays (if the "st += delay" calculation makes st small) and theoretically also unbound delays (if st ends up being UINT_MAX and one just misses sampling digctl_microseconds at that point). It doesn't take more code to DTRT, and once bitten, twice shy. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-01-07ARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methodsMichael Trimarchi
Engicam i.CoreM6 1.5 Quad/Dual MIPI dtsi is reusing fec node from Engicam i.CoreM6 dtsi but have sampe copy of phy-reset-gpio and phy-mode properties. So, drop this phy reset methods from imx6qdl-icore-1.5 dsti file. Cc: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-07ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DLJagan Teki
The EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation is based on the 1.5 version of the i.Core MX6 cpu module. The 1.5 version differs from the original one for a few details, including the ethernet PHY interface clock provider. With this commit, the ethernet interface works properly: SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver While before using the 1.5 version, ethernet failed to startup do to un-clocked PHY interface: fec 2188000.ethernet eth0: could not attach to PHY Similar fix has merged for i.Core MX6Q but missed to update for DL. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-07ARM: dts: icorem6: Sync engicam device trees from v5.4Jagan Teki
Sync Engicam device tree file from v5.4 linux-next. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-07arm: mxs: be more careful when enabling gpmi_clkRasmus Villemoes
The data sheet says that the DIV field cannot change while the CLKGATE bit is set or modified. So do it a little more carefully, by first clearing the bit, waiting for that to appear, then setting the DIV field. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-01-07arm: mxs: fix comments in arch_cpu_init to match the codeRasmus Villemoes
The comment says to clear the bypass bit, but in fact it sets it, thus selecting ref_xtal. And the next line of code does not set the divider to 12, but to (the reset value of) 1. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-01-07arm: mxs: fix register definitions for clkctrl_gpmi and clkctrl_sspXRasmus Villemoes
I tried clearing a bit by writing to hw_clkctrl_gpmi_clr, then busy-waiting for it to actually clear. My board hung. The data sheet agrees, these registers do not have _set, _clr, _tog, so fix up the definitions. git grep -E 'clkctrl_(gpmi|ssp[0-9])_' says that nobody uses those non-existing ops registers. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-01-07mach-imx: nandbcb: improve cmd helpIgor Opaniuk
Add info about supported i.MX7, improve details the usage of bcbonly subcommand. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07ddr: imx8m: Return error values from LPDDR4 trainingFrieder Schrempf
In cases when the same SPL should run on boards with i.MX8MM, that differ in DDR configuration, it is necessary to try different parameters and check if the training done by the firmware suceeds or not. Therefore we return the DDR training/initialization success to the upper layer in order to be able to retry with different settings if necessary. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2020-01-07arm: imx: Default to SYS_THUMB_BUILD for i.MX6/7Tom Rini
In the case of i.MX6 and i.MX7 family SoCs it is safe (from an errata point of view) to use thumb2 by default to save space. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-01-07mach-imx: bootaux: elf firmware supportIgor Opaniuk
Currently imx-specific bootaux command doesn't support ELF format firmware for Cortex-M4 core. This patches introduces a PoC implementation of handling elf firmware (load_elf_image_phdr() was copy-pasted from elf.c just for PoC). ELF64 binaries isn't supported yet. This has the advantage that the user does not need to know to which address the binary has been linked to. However, in order to handle and load the elf sections to the right address, we need to translate the Cortex-M4 core memory addresses to primary/host CPU memory addresses (Cortex A7/A9 cores). This allows to boot firmwares from any location with just using bootaux, e.g.: > tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr} Similar translation table can be found in the Linux remoteproc driver [1]. [1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07ARM: dts: imx7: imx7_colibri: introduce fec nodeIgor Opaniuk
Sync DTS with the mainline Linux and introduce fec node and regulator configuration for rn5t567 PMU. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07ARM: dts: imx6_apalis: introduce fec nodeIgor Opaniuk
Sync DTS with the mainline Linux and introduce fec node. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07ARM: dts: imx6_colibri: introduce fec nodeIgor Opaniuk
Sync DTS with the mainline Linux and introduce fec node. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-01-07mx7dsabre: Enable DM_ETHJoris Offouga
Also sync device tree with v5.5-rc1 Signed-off-by: Joris Offouga <offougajoris@gmail.com>
2020-01-07mx7ulp: Add support for Embedded Artists COM boardFabio Estevam
The Embedded Artists COM board is based on NXP i.MX7ULP. It has a BD70528 PMIC from Rohm with discrete DCDC powering option and improved current observability (compared to the existing NXP i.MX7ULP EVK). Add the initial support for the board. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-01-07imx: cx9020: migrate cx9020 to CONFIG_DM_USBSteffen Dirkwinkel
Note: gpio7_8 was never used for usb power regulator so we remove it here Acked-by: Patrick Bruenn <p.bruenn@beckhoff.com> Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
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