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2018-11-29dts: arm: socfpga: merge gen5 devicetrees from linuxSimon Goldschmidt
Add -u-boot.dtsi files to keep the current U-Boot behaviour: - add u-boot,dm-pre-reloc where required - disable watchdog - set uart clock frequency - add gpio bank-name properties where appropriate: - make qspi work (add alias for spi0, fix compatible for flash) - enable usb (status okay, add alias for udc0) Adapt board dts files that are not in Linux to keep their old behaviour. Change licenses to SPDX. (Patman warnings/errors are in 1:1 copied files from Linux) Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29spi: cadence_qspi: use "cdns,qspi-nor" as compatibleSimon Goldschmidt
Linux uses "cdns,qspi-nor" as compatible string for the cadence qspi driver, so change driver, docs and all device trees. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29arm: socfpga: make config structs constSimon Goldschmidt
There are two config structs left in wrap_sdram_config.c that can be made const. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29arm64: zynqmp: Setup clock-output-names for si570 chipsMichal Simek
If there are more instances of si570 clock-output-names property should be used for differentiation of clock output. The patch is adding this optional properties for all zynqmp boards with si570 chip. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29arm64: zynqmp: Disable ltc2952 poweroff chipMichal Simek
This chip is on the board but handling should be done via firmware not via Linux driver. Changing status property to keep it in the tree to describe it instead of removing this node completely. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29arm64: zynqmp: Fix sdhci clock in emmc0 mini configurationMichal Simek
Add missing clocks property. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29arm64: zynqmp: Wire spi-flash compatible string with flashesMichal Simek
Enable reading tx and rx buswidth from DT via spi-uclass. To get these from uclass spi-flash compatible string has to be added to flash node. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29arm64: zynqmp: Define and enable qspi node for DC4 boardSiva Durga Prasad Paladugu
DC4 board has qspi on it hence define and enable qspi node for it. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-28pinctrl: MediaTek: add pinctrl driver for MT7629 SoCRyder Lee
This patch adds pinctrl support for MT7629 SoC. The IO core found on the SoC has the registers for pinctrl, pinconf and gpio mixed up in the same register range. Hence the driver also implements the gpio functionality through UCLASS_GPIO. This also creates a common file as there might be other chips that use the same binding and driver, then being a little more abstract could help in the long run. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28arm: MediaTek: add basic support for MT7623 boardsWeijie Gao
This adds a general board file based on MT7623 SoCs from MediaTek. As this u-boot is loaded by MTK proprietary preloader, there is no low level initializtion codes. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28arm: MediaTek: add basic support for MT7629 boardsRyder Lee
This adds a general board file based on MT7629 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28arm: dts: MediaTek: add device tree for MT7623Ryder Lee
This adds device tree for MT7623 development board - Bananapi R2 Detailed hardware information for BPI-R2 which could be found on http://wiki.banana-pi.org/Banana_Pi_BPI-R2. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28arm: dts: MediaTek: add device tree for MT7629Ryder Lee
This patch adds MT7629 device tree and the includes it needs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-26ARM: dts: am335x-chiliboard: add /chosen/stdout-pathMarcin Niestroj
Add that node path in u-boot overlay dtsi file for now to keep am335x-chiliboard.dts in sync with Linux. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26ARM: dts: am335x-chili*: add chiliSOM and chiliboard DTS filesMarcin Niestroj
Import chiliSOM and chiliboard dts files from Linux v4.19. They will be used after transition to driver model and device-tree based boot. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26ARM: armv7: Add early stack for erratum workaroundsAndrew F. Davis
Some erratum workarounds call into C code before the stack is setup, this can lead to values pushed onto the stack being lost, firewall exceptions, and other undefined behavior. Setup a temporary stack to allow these functions to work correctly. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2018-11-26armv7r: K3: Allow SPL to run only on core 0Lokesh Vutla
Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode. If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode. If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2018-11-26ARM: meson: Add boot device discoveryNeil Armstrong
The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol. When no other boot medium are available (or by forcing the USB mode), the ROM sets the primary USB port as device mode and waits for a Host to enumerate. When enumerated, a custom protocol described at [1] permits writing to memory and execute some specific FIP init code to run the loaded Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage. In this mode, we can load different binaries that can be used by U-boot like a script image file. This adds support for a custom USB boot stage only available when the boot mode is USB and the script file at a pre-defined address is valid. This support was heavily copied from the Sunxi Allwinner FEL U-Boot support. The tool pyamlboot described at [2], permits using this boot mode on boards exposing the first USB port, either as OTG or Host port. [1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md [2] https://github.com/superna9999/pyamlboot/blob/master/README.md Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26ARM: meson: factorize common code out amlogic's boardsJerome Brunet
Now we have moved all the Amlogic board support to common generic board code, we can move the identical board_init() and ft_board_setup() functions to weak functions into the board-common mach-meson file. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26board: amlogic: add support for S400 boardNeil Armstrong
The S400 board is the Amlogic AXG SoC reference board including : - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz - 1GB DDR4 SDRAM - 10/100 Ethernet - 2 x USB 2.0 Host - eMMC - Infrared receiver - SDIO WiFi Module - MIPI DSI Connector - Audio HAT Connector - PCI-E M.2 Connectors Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26clk: Add clock driver for AXGNeil Armstrong
This patch adds a minimal clock driver for the Amlogic AXG SoC to handle the basic gates and PLLs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1Neil Armstrong
Synchronize the Amlogic AXG Device Tree files and bindings include from the recent Linux 4.20-rc1, because it includes patches fixing support for U-boot. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26ARM: meson: Add support for AXG familyNeil Armstrong
This patch adds support for the Amlogic AXG SoC, which is very close from the Amlogic GXL SoCs with : - Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max - DDR Interface limited to DDR4 16bit - The whole physical register address space has been moved to 0xfxxxxxxx - The pinctrl setup has changed - The clock tree is different enough to use a different driver Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26ARM: meson: rework soc arch file to prepare for new SoCJerome Brunet
We are about to add support for the Amlogic AXG SoC. While very close to the Gx SoC family, we will need to handle a few thing which are different in this SoC. Rework the meson arch directory to prepare for this. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26ARM: rework amlogic configurationJerome Brunet
Rework the board SYS_BOARD, SYS_VENDOR and SYS_CONFIG_NAME setup by moving the board Kconfig into the mach-meson Kconfig to make it easier to add new boards for a SoC architecture and add a custom config header or custom board handler for a platform. This drops the board CONFIGs and the duplicate boards configs headers in favor of a single meson64.h config header. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26board: amlogic: factorise gxbb boardsJerome Brunet
The nanopi-k2 and the odroid-c2 are similar enough to be supported by the same u-boot board. This change use odroid-c2 u-boot board for the nanopi-k2 as well. Dedicated defconfig are kept to customize the names and device tree. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26board: amlogic: move khadas-vim2 as q200 ref boardNeil Armstrong
The Khadas vim2 derive from amlogic s912 reference design (Q200). This patch moves the khadas-vim2 board support to a generic Q200 board, while keeping a dedicated defconfig to customize the names and device tree. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26board: amlogic: remove p212 derivativesJerome Brunet
The Khadas vim and the libretech aml-s905x-cc (aka Potato) derive from amlogic s905x reference design (P212). All the code in these board is a copy/paste from the p212, which is tedious to maintain. This change use p212 u-boot board for all these boards, while keeping a dedicated defconfig to customize the names and device tree. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26ARM: meson: clean-up platform selectionJerome Brunet
Even if multiple board are selected through Kconfig, u-boot will only compile one. This makes sense since compiling these targets will export global symbols, such as board_init() The change rework amlogic Kconfig so only one board may be selected at a time Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26arm64: zynqmp: Enable SPL_SEPARATE_BSS by defaultMichal Simek
BSS section was all the time separated for SPL but this symbol wasn't enabled. It is necessary to have it enabled for OF_SEPARATE configuration where DTB is appended to u-boot with DTB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26arm64: zynqmp: Reflect emmc controller ID in model in DTMichal Simek
Make sense to add controller ID to model name to have it visible through the logs to know which controller is used by which configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26arm: zynq: cse_qspi: Fix overwriting spi-rx-bus-width propertySiva Durga Prasad Paladugu
spi-rx-bus-width property is part of flash, so it should be moved to flash node from qspi node. This patch fixes the incorrect read of spi-rx-bus-width property by moving it to flash node. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-22sunxi: Fix memory 2-rank initialization for a33 cpuMichael Trimarchi
When we initialize the memory we need to autodetect rank and size but this can happen only if we send the proper reset to both memory module including cke signal. For this reason we need initialize the physical on both channel because we need to presume that both are connected. This way let the CLKE to be activated at the right time with the memory reset coming from the cpu Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-22sunxi-mmc: use new mode on both controllers on A64Vasily Khoruzhick
Using new mode improves stability of eMMC and SD cards. Without it SPL fails to load u-boot from SD on Pinebook. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-22sunxi-mmc: introduce new MMC_SUNXI_HAS_MODE_SWITCH optionVasily Khoruzhick
Allwinner A64 has new mode but doesn't have a mode switch in CCM, and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails if MMC_SUNXI_HAS_NEW_MODE is enabled Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage of CCM_MMC_CTRL_MODE_SEL_NEW Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> [jagan: update commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
2018-11-20misc: Update read() and write() methods to return bytes xferedSimon Glass
At present these functions return 0 on success. For some devices we want to know how many bytes were transferred. It seems useful to adjust the API to be more like the POSIX read() and write() functions. Update these two methods, a test and all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-20ARM: mvebu: dts: add Clearfog GT-8KRabeeh Khoury
The SolidRun Clearfog GT-8K is based on Armada 8040. https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k The config file is identical to the Macchiatobin one (mvebu_mcbin-88f8040_defconfig) with only the default device-tree changed. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20arm64: mvebu: a8k: autodetect RAM sizeBaruch Siach
Some Armada 8K boards like Macchiatobin and Clearfog GT-8K use RAM from external DIMM. Hard coding the RAM size in the device-tree is not convenient. Fortunately, the ATF that initializes the RAM knows the size of RAM, and U-Boot can query the ATF using a SMC call. The ATF maps the lower 3G of RAM starting at address 0. Higher RAM is mapped at 4G. This leaves a 1G hole between 3G and 4G for IO peripherals. Use a second bi_dram[] entry to describe the higher RAM area. As a result, CONFIG_NR_DRAM_BANKS must be set to 2 to use more than 3GB RAM. This code in this commit is mostly taken from downstream Marvell U-Boot code by Grzegorz Jaszczyk. Cc: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20linux/sizes.h: sync from kernelBaruch Siach
The kernel added SZ_4G macro in commit f2b9ba871b (arm64/kernel: kaslr: reduce module randomization range to 4 GB). Include linux/const.h for the _AC macro. Drop a local SZ_4G definition in tegra code. Cc: Tom Warren <twarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20Use _AC and UL macros from linux/const.hBaruch Siach
Drop the _AC and UL macros from common.h. Linux headers is the original source of this macro, so keep its definition in the same header. Update existing users of these macros to include const.h directly. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Rick Chen <rick@andestech.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-16armv7r: dts: am654: Add initial supportLokesh Vutla
Add R5 specific dts for am654-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-16arm: dts: k3: Sync dts from LinuxLokesh Vutla
Sync the k3-am654 specific dts files from Linux next with tag 20181019. This changes are in queue for Linux v4.20-rc1 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16armv7R: K3: am654: Add support for triggering ddr init from SPLLokesh Vutla
In SPL, DDR should be made available by the end of board_init_f() so that apis in board_init_r() can use ddr. Adding support for triggering DDR initialization from board_init_f(). Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16armv7R: K3: am654: Add support to start ATF from R5 SPLLokesh Vutla
Considering the boot time requirements, Cortex-A core should be able to start immediately after SPL on R5. Add support for the same. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16armv7R: K3: am654: Add support for generating build targetsLokesh Vutla
Update Makefiles to generate: - tiboot3.bin: Image format that can be processed by ROM. Below is the tiboot3.bin image format that is required by ROM: _______________________ | X509 | | Certificate | | ____________________ | | | | | | | u-boot-spl.bin | | | | | | | |___________________| | |_______________________| Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2018-11-16armv7R: K3: am654: Enable MPU regionsLokesh Vutla
Enable MPU regions for AM654 evm: - Region0: 0x00000000 - 0xFFFFFFFF: Device memory, not executable - Region1: 0x41c00000 - 0x42400000: Normal, executable, WB, Write alloc - Region2: 0x80000000 - 0xFFFFFFFF: Normal, executable, WB, Write alloc - region3-15: Disabled With this dcache can be enabled either in SPL or U-Boot. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16ram: Introduce K3 AM654 DDR Sub System driverLokesh Vutla
K3 based AM654 devices has DDR memory subsystem that comprises Synopys DDR controller, Synopsis DDR phy and wrapper logic to intergrate these blocks into the device. This DDR subsystem provides an interface to external SDRAM devices. Adding support for the initialization of the external SDRAM devices by configuring the DDRSS registers and using the buitin PHY routines. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com>
2018-11-16arm: Make arch specific memcpy thumb-safe.Klaus Goger
The current arch implementation of memcpy cannot be called from thumb code, because it does not use bx instructions on return. This patch addresses that. Note, that this patch does not touch the hot loop of memcpy, so performance is not affected. Tested on MXS (arm926ejs) with and without thumb-mode enabled. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
2018-11-16ARM: DTS: Resync am3517-evm.dts with Linux 4.19Adam Ford
Some minor changes have been made to the AM3517-evm and the underlying am3517.dtsi files. This patch re-sync's the DTS and DTSI files with Linux. Signed-off-by: Adam Ford <aford173@gmail.com>