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2017-11-28arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3Anurag Kumar Vulisha
This patch adds support for reading silicon revision using zynqmp nvmem driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Move nodes which have no reg property out of busMichal Simek
Nodes without reg properties shouldn't be placed in amba node. Move them out. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: dt: Add AMS nodeMichal Simek
The AMS includes an ADC as well as on-chip sensors that can be used to sample external voltages and monitor on-die operating conditions, such as temperature and supply voltage levels. Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 siliconManish Narani
This patch sets host quirk2 bit field for No 1.8V supported in case of 1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This property will ensure the SD runs on High Speed mode. Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Use reset controller framework for asserting/de-asserting resetAnurag Kumar Vulisha
This patch modifies the phy_zynqmp.c driver to use reset-controller framework for asserting/de-asserting reset for High Speed modules. Also fix documentation and dtsi. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add reset-controller support in serdes driverAnurag Kumar Vulisha
This patch add the reset nodes in zynqmp.dtsi which are used by reset-controller framework Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove tx_termination_fix detection on silicon v1Michal Simek
Only silicon v1 requires this termination fix. With new nvmem soc revision nvmem detection driver this can be autodetected at run time and this flag is not needed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add support for zynqmp nvmem firmware driverNava kishore Manne
Add support for zynqmp nvmem firmware driver. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add support for zcu102 1.0 revMichal Simek
1.0 rev is the latest rev. Describe information in eeprom. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Update device tree for pinmuxMichal Simek
Added pin control support in device tree for zynqmp. Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove local-mac-address from dtsi fileMichal Simek
Generic dtsi file can't use the same mac address for all. U-Boot read mac from eeprom in zcu102 case and for others random mac address is generated. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Use SPDX license with dc4Michal Simek
Just header change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove leading 0s from mtd table for spi flashesMichal Simek
dtc reports issues with it. arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning (unit_address_format): Node /amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning (unit_address_format): Node /amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (unit_address_format): Node /amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (unit_address_format): Node /amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should not have leading 0s Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add missing alias for gem0 for ep108Michal Simek
Add missing alias for gem0 for ep108 to have proper sequence number. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIeBharat Kumar Gogada
- Enabling GTR lane-0 to PCIe - Enabling PCIe node in device tree Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Update device tree for gpioChirag Parekh
Used defines rather than raw values for gpio configurations. Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add revB string to compatible stringMichal Simek
Some user space libraries reading platform compatible string and based on that changing behavior. Mark revB board with revB string. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Use revision in dts file descriptionMichal Simek
Trivial change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: PM: Specify power domains for DP related nodesJyotheeswar Reddy Mutthareddyvari
Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is causing genpd to trigger a power down request for DP domain, making all DP related peripherals unusable. So assign power domains for all DP related nodes to enable proper accounting of DP power domain usage. Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: disable smmuNaga Sureshkumar Relli
This patch disables the smmu and also removes the mmu-masters Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: rtc: Add calibrationNava kishore Manne
This patch adds the calibration property with required value, calculated based on rtc input crystal oscillator frequency (32.768Khz). Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add SMMU support for SATA IPAnurag Kumar Vulisha
AXI master interface in CEVA AHCI controller requires two unique Write/Read ID tags per port. This is because, ahci controller uses different AXI ID[3:0] bits for identifying non-data transfers(like reading descriptors, updating PRD tables, etc) and data transfers (like sending/receiving FIS).To make SMMU work with SATA we need to add correct SMMU stream id for SATA. SMMU stream id for SATA is determined based on the AXI ID[1:0] as shown below SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0] Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so SMMU ID = 001, 0011, 00, 00, AXI ID[1:0] Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1 as said above) we get four different SMMU stream id's combinations for SATA. These AXI ID can be configured using PAXIC register. In this patch we assumed the below AXI ID values Read ID/ Write ID for Non-Data Port0 transfers = 0 Read ID/ Write ID for Data Port0 transfers = 1 Read ID/ Write ID for Non-Data Port1 transfers = 2 Read ID/ Write ID for Data Port1 transfers = 3 Based on the above values,SMMU stream ID's for SATA will be 0x4c0 & 0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be added to iommus dts property. This patch does the same. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: dts: xilinx: fix PCI bus dtc warningsRob Herring
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add missing gpio property to dtsiMichal Simek
All gpio controllers should contain this property. This property is not checked by the code that's why this issue wasn't found earlier. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Update the GPU address sizeHyun Kwon
The correct register size is 0x10000, otherwise it overlaps with other register space. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add clock name for GPUMadhurkiran Harikrishnan
This patch will add names to the clocks used by GPU. Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Label whole PL part as fpga_full regionNava kishore Manne
This will simplify dt overlay structure for the whole PL. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Fix broken architected timer interrupt triggerMichal Simek
Extract from Linux mainline patch: The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: PM: Add IRQSoren Brinkmann
PM callbacks are delivered to the NS OS. Let the PM driver handle the IRQ and retrieve callback data from the secure HW. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Reduced min-residency time for idle state nodeJolly Shah
Changed min-residence to 10ms(was 100 ms) for cpu-sleep-0. Tried lower values 5ms and 8ms and it worked fine with Debug Off. But to accommodate PM Debug On case, 10 ms is required. With this change, low power idle state is into effect more frequently. Measured boot time with PM debugs On and Off. No change observed compared to 100ms value. Signed-off-by: Jolly Shah <jollys@xilinx.com> Acked-by: Will Wong <willw@xilinx.com> Tested-by: Koteswararao Nayudu <kotin@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: DT: Fix typo in idle-states node definitionJyotheeswar Reddy
Fixed a typo in specifying "entry-method" Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Update the OPPs for cpu freqShubhrajyoti Datta
Add operating-points-v2. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add references to cpu nodesMichal Simek
Add missing references to all cpu nodes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Wire QSPI boot mode for SPLMichal Simek
ZynqMP qspi driver is on the way to mainline Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add support for CG/EG/EV device detectionMichal Simek
Version string has unused fields 31:20 which can be used for exporting 9 bits from efuse IPDISABLE regs to recognize eg/cg/ev devices. These efuse bits are setup for certain devices. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add SD1 level shifter mode to alternative selectionMichal Simek
Extend Kconfig to cover SD1 level shifter mode. Reported-by: Jason Wu <jason.hy.wu@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Enable config DEFINE_TCM_OCM_MMAP if CONFIG_MP definedSiva Durga Prasad Paladugu
This modifies default value of config DEFINE_TCM_OCM_MMAP to yes if CONFIG_MP is defined MP supports needs OCM and TCM part of memory map. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28tools: mkimage: Extend mkimage to also include pmufwMichal Simek
The patch is adding external pmufw "Platform Management Unit firmware" to boot.bin image. Boot.bin is a Xilinx format which bootrom is capable to read and boot the system. pmufw is copied to the header data section follows by u-boot-spl.bin. pmufw is consumed by PMU unit (Microblaze) and SPL runs on a53-0. This is generated command line when PMUFW_INIT_FILE is setup. ./tools/mkimage -T zynqmpimage -R ./"" -n ./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm64: zynqmp: Provide a Kconfig option to use specified memory for MMU tableSiva Durga Prasad Paladugu
This patch provides a Kconfig option to use specified memory for MMU table using reserve_mmu platform specific routine. Here we used TCM space for MMU table. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: mp: Correct the R5 release sequenceSiva Durga Prasad Paladugu
This patch corrects the R5 release sequence by adding the below steps. 1. Flush dcache to ensure that image loaded into memory. 2. Keep R5 reset just to ensure R5 in reset. 3. Disable caches before accessing TCM as with out this A53 can do speculative and may result in ECC failures if TCM's are not initialized. So, it is always better to disable dcaches before accessing TCM and enable back. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reported-by: John Linn <linnj@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove slcr with mio status pin detectionMichal Simek
This code is not used on this platform and it is not called. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Add mini u-boot configuration for zynqMichal Simek
Add configuration files/dtses for mini u-boot configurations which runs out of OCM. ram top is calculated from 0 that's why +#define CONFIG_SYS_SDRAM_BASE 0xfffc0000 +#define CONFIG_SYS_SDRAM_SIZE 0x40000 was hardcoded. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm: zynq: Sort dts namesMichal Simek
Sort names. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm: zynq: Add board support for cc108Michal Simek
cc108 board is wiring uart via PL which is good platform for SPL fpga support. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28arm: zynq: Sync location of DT properties with LinuxMichal Simek
This is trival change which only ensures the same location with Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Add device-type property for zynq ethernet phy nodesSai Pavan Boddu
Mention device-type = "ethernet-phy", as qemu will need this in absence of compatible. Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Add SCL & SDA GPIO entries for recoveryChirag Parekh
Wire i2c pinmuxing gpio recovery for zc702. Signed-off-by: Chirag Parekh <chiragp@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm: zynq: Add support for SYZYGY Hub boardTom McLeod
Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports booting from SD. Signed-off-by: Tom McLeod <tom.mcleod@opalkelly.com> Cc: Michal Simek <monstr@monstr.eu> CC: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: remove unnecessary logical constraintHeinrich Schuchardt
In if (a || b) else if (!a) the constraint (!a) is always true if else is reached and can be removed. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-27Merge git://www.denx.de/git/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit (git 2.34.1) at 2024-12-27 12:08:03 +0000