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2017-11-29clk: stm32fx: migrate define from rcc.h to driverPatrice Chotard
STM32F4 doesn't get rcc.h file, to avoid compilation issue, migrate RCC related defines from rcc.h to driver file and remove rcc.h file. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29ARM: DTS: stm32: update rcc compatible for STM32F746Patrice Chotard
Align the RCC compatible string with the one used by kernel. It will allow to use the same clock driver for STM32F4 and STM32F7 and to manage the differences between the 2 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32f7: retrieve PWR base address from DTPatrice Chotard
PWR IP is used to enable over-drive feature in order to reach a higher frequency. Get its base address from DT instead of hard-coded value Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29ARM: DTS: stm32: add pwrcfg node for stm32f746Patrice Chotard
This node is needed to enable performance mode when system frequency is set up to 200Mhz. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini u-boot configurations (cse) - dts updates - config/defconfig updates in connection to Kconfig changes - Fix psu_init handling ZynqMP: - SPL fixes - Remove slcr.c - Fixing r5 startup sequence - Add support for external pmufw - Add support for new ZynqMP chips - dts updates - Add support for zcu102 rev1.0 board Drivers: - nand: Support external timing setting and board init - ahci: Fix wording - axi_emac: Wait for bit, non processor mode, readl/write conversion - zynq_gem: Fix SGMII/PCS support
2017-11-29arm: zynq: Change Zynq/ZynqMP Kconfig descriptionMichal Simek
Use more accurate description for Xilinx Zynq and ZynqMP based platforms. With using driver model there shouldn't be a need to create separate Kconfig config options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29mtd: zynq: nand: Move board_nand_init() function to board.cWilson Lee
Putting board_nand_init() function inside NAND driver was not appropriate due to it doesn't allow board vendor to customise their NAND initialization code such as adding NAND lock/unlock code. This commit was to move the board_nand_init() function from NAND driver to board.c file. This allow customization of board_nand_init() function. Signed-off-by: Wilson Lee <wilson.lee@ni.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Cc: Scott Wood <oss@buserror.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29arm: zynq: Use unsigned type with comparison with ARRAY_SIZEMichal Simek
Sparse is return warning about this: arch/arm/mach-zynq/slcr.c: In function 'zynq_slcr_get_mio_pin_status': arch/arm/mach-zynq/slcr.c:185:16: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { ^ Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29arm: zynq: Add support for EMIT_WRITE operationMichal Simek
Add proper support for EMIT_WRITE operation which is write only. Do not use EMIT_MASKWRITE which is read-modify-write. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_initMichal Simek
Unfortunately camelcase is coming from ps7_init* format. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29arm: zynq: Move common ps7_init* initialization to arch codeMichal Simek
This patch is based on work done in topic board where the first address word also storing operation which should be done. This is reducing size of configuration data. This patch is not breaking an option to copy default ps7_init_gpl* files from hdf file but it is doing preparation for ps7_init* consolidation. The patch is also marking ps7_config as weak function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29arm: zynq: Move ps7_* to separate fileMichal Simek
Extract ps7_* from spl code to prepare for extension. And also return value. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29arm: zynq: Add missing ps7_post_config declarationMichal Simek
Add missing declaration to header. Warning log: arch/arm/mach-zynq/spl.c:94:12: warning: symbol 'ps7_post_config' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-29ARM: dts: uniphier: Sync with Linux 4.15-rc1Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29ARM: uniphier: remove XIRQ pin settingsMasahiro Yamada
The XIRQ pins are now set up on the Linux side by the GPIO hogging. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29ARM: uniphier: remove IRQ settingsMasahiro Yamada
This work-around has been here in U-Boot because the AIDET and GPIO drivers were missing in the upstream Linux. Both are now available in Linus' tree: - drivers/irqchip/irq-uniphier-aidet.c - drivers/gpio/gpio-uniphier.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-29bitops: collect BIT macros to include/linux/bitops.hMasahiro Yamada
Same macros are defined in various places. Collect them into include/linux/bitops.h like Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-11-28arm64: zynqmp: Enable watchdog by defaultShubhrajyoti Datta
Enable watchdog in dts for zcu102. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add note about si5328 interruptMichal Simek
Add comment about irq present on the board connected to PL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: usb: Correct IOMMU node for making SMMU work with USBAnurag Kumar Vulisha
This patch makes SMMU work by moving the iommus node under the dwc3 child entry from parent node. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove clock setting from dtsiMichal Simek
clock setting is handled via clk dtsi file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Uncomment snps,quirk-frame-length-adjustment flag in dwc3Anurag Kumar Vulisha
This patch uncomments snps,quirk-frame-length-adjustment which has the value to adjust the SOF/ITP generated from the controller. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add USB OTG interrupts support in dtManish Narani
This patch adds OTG interrupt support in device tree. It will add an extra interrupt line number dedicated to OTG events. This will enable OTG interrupts to serve in DWC3 OTG driver. Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Enabled CCI support for USBManish Narani
This patch adds CCI support for USB when CCI is enabled in design. This patch also adds 'reg' property for Xilinx USB 3.0 IP. The 'reg' property is added in order to modify a register in that to enable coherency in Hardware. Also add address to unit name to avoid dtc warning Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3Anurag Kumar Vulisha
This patch adds support for reading silicon revision using zynqmp nvmem driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Move nodes which have no reg property out of busMichal Simek
Nodes without reg properties shouldn't be placed in amba node. Move them out. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: dt: Add AMS nodeMichal Simek
The AMS includes an ADC as well as on-chip sensors that can be used to sample external voltages and monitor on-die operating conditions, such as temperature and supply voltage levels. Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 siliconManish Narani
This patch sets host quirk2 bit field for No 1.8V supported in case of 1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This property will ensure the SD runs on High Speed mode. Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Use reset controller framework for asserting/de-asserting resetAnurag Kumar Vulisha
This patch modifies the phy_zynqmp.c driver to use reset-controller framework for asserting/de-asserting reset for High Speed modules. Also fix documentation and dtsi. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add reset-controller support in serdes driverAnurag Kumar Vulisha
This patch add the reset nodes in zynqmp.dtsi which are used by reset-controller framework Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove tx_termination_fix detection on silicon v1Michal Simek
Only silicon v1 requires this termination fix. With new nvmem soc revision nvmem detection driver this can be autodetected at run time and this flag is not needed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add support for zynqmp nvmem firmware driverNava kishore Manne
Add support for zynqmp nvmem firmware driver. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add support for zcu102 1.0 revMichal Simek
1.0 rev is the latest rev. Describe information in eeprom. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Update device tree for pinmuxMichal Simek
Added pin control support in device tree for zynqmp. Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove local-mac-address from dtsi fileMichal Simek
Generic dtsi file can't use the same mac address for all. U-Boot read mac from eeprom in zcu102 case and for others random mac address is generated. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Use SPDX license with dc4Michal Simek
Just header change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Remove leading 0s from mtd table for spi flashesMichal Simek
dtc reports issues with it. arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning (unit_address_format): Node /amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning (unit_address_format): Node /amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (unit_address_format): Node /amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (unit_address_format): Node /amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should not have leading 0s Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add missing alias for gem0 for ep108Michal Simek
Add missing alias for gem0 for ep108 to have proper sequence number. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIeBharat Kumar Gogada
- Enabling GTR lane-0 to PCIe - Enabling PCIe node in device tree Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Update device tree for gpioChirag Parekh
Used defines rather than raw values for gpio configurations. Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add revB string to compatible stringMichal Simek
Some user space libraries reading platform compatible string and based on that changing behavior. Mark revB board with revB string. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Use revision in dts file descriptionMichal Simek
Trivial change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: PM: Specify power domains for DP related nodesJyotheeswar Reddy Mutthareddyvari
Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is causing genpd to trigger a power down request for DP domain, making all DP related peripherals unusable. So assign power domains for all DP related nodes to enable proper accounting of DP power domain usage. Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: disable smmuNaga Sureshkumar Relli
This patch disables the smmu and also removes the mmu-masters Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: rtc: Add calibrationNava kishore Manne
This patch adds the calibration property with required value, calculated based on rtc input crystal oscillator frequency (32.768Khz). Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add SMMU support for SATA IPAnurag Kumar Vulisha
AXI master interface in CEVA AHCI controller requires two unique Write/Read ID tags per port. This is because, ahci controller uses different AXI ID[3:0] bits for identifying non-data transfers(like reading descriptors, updating PRD tables, etc) and data transfers (like sending/receiving FIS).To make SMMU work with SATA we need to add correct SMMU stream id for SATA. SMMU stream id for SATA is determined based on the AXI ID[1:0] as shown below SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0] Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so SMMU ID = 001, 0011, 00, 00, AXI ID[1:0] Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1 as said above) we get four different SMMU stream id's combinations for SATA. These AXI ID can be configured using PAXIC register. In this patch we assumed the below AXI ID values Read ID/ Write ID for Non-Data Port0 transfers = 0 Read ID/ Write ID for Data Port0 transfers = 1 Read ID/ Write ID for Non-Data Port1 transfers = 2 Read ID/ Write ID for Data Port1 transfers = 3 Based on the above values,SMMU stream ID's for SATA will be 0x4c0 & 0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be added to iommus dts property. This patch does the same. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: dts: xilinx: fix PCI bus dtc warningsRob Herring
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add missing gpio property to dtsiMichal Simek
All gpio controllers should contain this property. This property is not checked by the code that's why this issue wasn't found earlier. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Update the GPU address sizeHyun Kwon
The correct register size is 0x10000, otherwise it overlaps with other register space. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28arm64: zynqmp: Add clock name for GPUMadhurkiran Harikrishnan
This patch will add names to the clocks used by GPU. Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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