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2014-10-23keystone2: msmc: add MSMC cache coherency support for K2L SOCHao Zhang
This patch adds Keystone II Lamar (K2L) SoC specific definitions to support MSMC cache coherency. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23keystone2: clock: add K2L clock definitions and commandsHao Zhang
This patch adds clock definitions and commands to support Keystone II K2L SOC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23ARM: keystone2: add K2L device hardware definitionsHao Zhang
This patch adds hardware definitions specific to Keystone II Lamar (K2L) SoC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23ARM: cmd_clock: generalize command usage descriptionKhoronzhuk, Ivan
The usage description of commands refers to headers of sources, that is not correct. This patch is intended to fix it. Also generalize code in order to reduce SoC dependent #ifdefs. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23keystone: usb: add support of usb xhciWingMan Kwok
Add support of usb xhci. xHCI controls all USB speeds of the Host mode, that is, the SS through the SS PHY, as well as the HS, FS, and LS through the USB2 PHY. xHCI replaces and supersedes all previous host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not backwards compatible with any of them. The USB3SS’s USB Controller is fully compliant with xHC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23dma: keystone_nav: generalize driver usageKhoronzhuk, Ivan
The keystone_nav driver is general driver intended to be used for working with queue manager and pktdma for different IPs like NETCP, AIF, FFTC, etc. So the it's API shouldn't be named like it works only with one of them, it should be general names. The names with prefix like netcp_* rather do for drivers/net/keystone_net.c driver. So it's good to generalize this driver to be used for different IP's and delete confusion with real NETCP driver. The current netcp_* functions of keystone navigator can be used for other settings of pktdma, not only for NETCP. The API of this driver is used by the keystone_net driver to work with NETCP, so net driver also should be corrected. For convenience collect pkdma configurations in drivers/dma/keystone_nav_cfg.c. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23dma: keystone_nav: move keystone_nav driver to driver/dma/Khoronzhuk, Ivan
The keystone_nav is used by drivers/net/keystone_net.c driver to send and receive packets, but currently it's placed at keystone arch sources. So it should be in the drivers directory also. It's separate driver that can be used for sending and receiving pktdma packets by others drivers also. This patch just move this driver to appropriate directory and doesn't add any functional changes. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23keystone2: keystone_nav: don't use hard addresses in netcp_pktdmaKhoronzhuk, Ivan
Use definitions in netcp_pktdma instead direct addresses. The definitions can be set specifically for SoC, so there is no reason to check SoC type while initialization. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23keystone2: keystone_nav: don't use hard addresses in qm_configKhoronzhuk, Ivan
Use definitions in qm_config. The definitions can be set specifically for SoC, so there is no reason to check SoC type while initialization. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-22dm: rpi: Convert GPIO driver to driver modelSimon Glass
Convert the BCM2835 GPIO driver to use driver model, and switch over Raspberry Pi to use this, since it is the only board. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2014-10-22dm: imx: i2c: Use gpio_request() to request GPIOsSimon Glass
GPIOs should be requested before use. Without this, driver model will not permit the GPIO to be used. Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2014-10-22imx: Add error checking to setup_i2c()Simon Glass
Since this function can fail, check its return value. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-10-22dm: tegra: spi: Convert to driver modelSimon Glass
This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: tegra: dts: Add aliases for spi on tegra30 boardsSimon Glass
All boards with a SPI interface have a suitable spi alias except the tegra30 boards. Add these missing aliases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22exynos: universal_c210: Move to driver model soft_spiSimon Glass
Adjust this board to use the driver model soft_spi implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22dm: exynos: Convert SPI to driver modelSimon Glass
Move the exynos SPI driver over to driver model. This removes quite a bit of boilerplate from the driver, although it adds some for driver model. A few device tree additions are needed to make the SPI flash available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22dm: exynos: Mark exynos5 console as pre-relocSimon Glass
We will need the console before relocation, so mark it that way. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: exynos: gpio: Convert to driver modelSimon Glass
Convert the exynos GPIO driver to driver model. This implements the generic GPIO interface but not the extra Exynos-specific functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: exynos: Make sure that GPIOs are requestedSimon Glass
With driver model GPIOs must be requested before use. Make sure this is done correctly. (Note that the soft SPI part of universal is omitted, since this driver is about to be replaced with a driver-model-aware version) Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: exynos: Tidy up GPIO headersSimon Glass
The wrong header is being included, thus requiring the code to re-declare the generic GPIO interface in each GPIO header. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: exynos: Add pinctrl settings for s5p_goniSimon Glass
These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: exynos: Add pinctrl settings for smdkc100Simon Glass
These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: exynos: dts: Adjust device tree files for U-BootSimon Glass
The pinctrl bindings used by Linux are an incomplete description of the hardware. It is possible in most cases to determine the register address of each, but not in all cases. By adding an additional property we can fix this, and avoid adding a table to U-Boot for every single Exynos SOC. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: exynos: dts: Remove unused pinctrl information to save spaceSimon Glass
We don't include the pinctrl functions for U-Boot as they use up quite a bit of space and are not used. We could instead perhaps eliminate this material with fdtgrep, but so far this tool has not made it to upstream. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: exynos: Bring in pinctrl dts files from Linux kernelSimon Glass
Bring in required device tree files for pinctrl from Linux v3.14. These are initially unchanged and have a number of pieces not needed by U-Boot. Note that exynos5420 is renamed to exynos54xx here since we want to support exynos5422 also. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22dm: exynos: dts: Convert /include/ to #includeSimon Glass
We should be consistent about this. The kernel has moved to #include which breaks error reporting to some extent but does allow us to include binding files. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-16ls102x: configs - Add hash command in freescale LS1 platformsRuchika Gupta
Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-11Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-10-10ARM: keystone: clock: fix main pll ratio div definitionsKhoronzhuk, Ivan
The definitions for div ratio supposed to be in hex and were added in dec by mistake. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-10ARM: OMAP5+: sata: Move scsi_scan() to the right placeRoger Quadros
scsi_scan() must be called as part of scsi_init() and not as part of sata_init(). Signed-off-by: Roger Quadros <rogerq@ti.com>
2014-10-10OMAP5+: sata/scsi: Implement scsi_init()Roger Quadros
On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: Roger Quadros <rogerq@ti.com>
2014-10-10Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-10-09arm: rmobile: r8a7794: Skip initialize L2 cacheNobuhiro Iwamatsu
rmobile/lowlevel_init_ca15.S are common in r8a7790, r8a7791 and r8a7794 of rmobile SoCs. The initialize L2 cache in lowlevel_init_ca15.S only needed for Cortex-A15. The r8a7794 is Cortex-A7, not Cortex-A15. This adds Skip to initialize L2 cache when r8a7794. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-10-09arm: rmobile: r8a7791: Fix initialize L2 cacheNobuhiro Iwamatsu
rmobile/lowlevel_init_ca15.S are common in r8a7790 and r8a7791 of rmobile SoC. But L2 cache of r8a7791 does not use L2CTLR[5]. This adds fix to set L2CTLR [5] only when the r8a7790. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-10-09arm: rmobile: Remove unnecessary initialization for l2ctlrNobuhiro Iwamatsu
This removes duplicate initialization of l2ctlr. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-10-08Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD
The single file conflict below is actually trivial. Conflicts: board/boundary/nitrogen6x/nitrogen6x.c
2014-10-08armv7: s5pc1xx: improve cache handlingRobert Baldyga
Move cache handling code to C file, and add enable_caches() and disable_caches() functions. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-08samsung: Enable device tree for smdkc100Simon Glass
Change this board to add a device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-08samsung: Enable device tree for s5p_goniSimon Glass
Change this board to add a device tree. This also adds a pinmux header file although it is not used as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-08config: Move smdkv310 to use common exynos4 fileSimon Glass
Most of the smdkv310 features are common with other exynos4 boards. To permit easier addition of driver model support, use the common file and add a device tree file. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-08exynos: dts: Add device tree node for cros_ec keyboardSimon Glass
Add a keyboard definition so that the keyboard can be used on pit. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-08Exynos: Use 900MHz ARM frequency in SPL for peach_pitSimon Glass
The device seems to hang in SPL if the full speed is used when booting from USB, perhaps because the PMIC has not been set to the maximum ARM core voltage yet. Slow it down to a reliable speed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-10-07Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-10-07vf610twr: Tune DDR initialization settingsAnthony Felice
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice <tony.felice@timesys.com> [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-10-06arm: socfpga: Add command to control HPS-FPGA bridgesMarek Vasut
Add command to enable and disable the bridges between HPS and FPGA. This patch does have a checkpatch issue with the assembler portion, checkpatch correctly complains that there should be no whitespace before quoted newline. I do not agree that fixing this specific checkpatch issue will improve the readability, thus this one is not addressed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
2014-10-06arm: socfpga: Move cache_enable to CPU codeMarek Vasut
Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: nic301: Add NIC-301 configuration codePavel Machek
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA . The code sets the access permissions for the CPU to the AMBA slaves such that the CPU can access them in both secure and non-secure mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: pl310: Map SDRAM to 0x0Marek Vasut
Configure the PL310 address filter to make sure DRAM is mapped to 0x0. This code also configures the "remap" register of NIC-301 and sets the required 'mpuzero' bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: nic301: Add NIC-301 GPV register fileMarek Vasut
Add register definition for the NIC-301 used on SoCFPGA. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: scu: Add SCU register fileMarek Vasut
Add the Snoop Control Unit register definition file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
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