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2018-12-07sunxi: pmic_bus: Decrease boot time by not writing duplicate dataOlliver Schinagl
When we clear a pmic_bus bit, we do a read-modify-write operation. We waste some time however, by writing back the exact samea value that was already set in the chip. Let us thus only do the write in case data was changed. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-07arm: socfpga: imply SPL options instead of selectSimon Goldschmidt
For a small SPL, it should be possible to build without SPI(-flash) drivers or wihout MMC drivers. For this to work, we have to change from 'select'ing options to 'imply'ing them. With this change, I can have SPL trimmed to my hard-wired starting method (SPI-NOR or MMC) while still including all drivers in U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-12-07dts: dra7x: make ocp2scp@4a080000 compatible with simple-busJean-Jacques Hiblot
This is required when DM_USB is used, to bind the USB phys. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07usb: introduce a separate config option for DM USB deviceJean-Jacques Hiblot
Using CONFIG_DM_USB for this purpose prevents using DM_USB for host and not for device. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2018-12-07ARM: rmobile: Fix to enable icache early in Gen3Takeshi Kihara
This patch fixes the problem that u-boot will not start unless icache is enabled early. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07ARM: rcar_gen3: fix protection area access errorTakeshi Kihara
This patch fixes the problem that "main memory domain AXI secure access protection error" occurs. Exclude the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07ARM: rcar_gen3: fix protection area access error at Cortex-A53Hiroyuki Yokoyama
This patch fixes the problem that "main memory domain AXI secure access protection error" occurs when booting Cortex-A53. Exclude the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07arm: dts: am33xx: Sync dts with Linux 4.20.0Felix Brack
This patch synchronizes the am33xx SoC specific files with those from Linux 4.20.0. Hence all board maintainers of am33xx based boards are on the cc list. The main purpose of this patch is to prevent further diverging of the dts files from U-Boot and those from Linux. It aims to set the stage for the synchronization of board specific dts files. Example: I'm the maintainer of the PDU001 board: once this patch is applied successfully I will make changes to the board specific dts file in Linux only and then post a patch with a copy of this exact dts file to U-Boot. This will make U-Boot and Linux remain in sync. The stumbling block of https://patchwork.ozlabs.org/patch/943627 was removed by the patch https://patchwork.ozlabs.org/patch/962428 from Lokesh Vutla (many thanks!). This omap-serial driver allows using the Linux am33xx.dtsi file in U-Boot. Other changes to dts and dtsi files made by this patch are mainly to prevent _new_ warnings during the build process. Especially the warning at pinmux@800 stating 'unnecessary #address-cells/#size-cells without "ranges" or child "reg"' was not removed. This warning is a good example showing the benefit of the synchronization: if it needs to be fixed it will be fixed in Linux and ported back to U-Boot. Buildman reports all 46 am33xx SoC based boards to build fine, with warnings of course. Nevertheless this patch should be tested thoroughly on as many boards as possible to prevent any collateral damage. Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07ARM: DTS: da850-evm: Re-sync da850-evm.dts from Linux 4.20Adam Ford
There has been some natural evolution of the device tree, so resync with 4.20 Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07ARM: dts: da850-lcdk: Sync from Linux 4.20Adam Ford
Re-synce the device tree files from Linux 4.20 Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07ARM: DTS: da850: Sync from Linux 4.20Adam Ford
Re-sync with 4.20 due some some natural evolution. Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit with Linux 4.20Adam Ford
Migrate some small device tree fixes from Linux 4.20. Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07ARM: DTS: Resync LogicPD SOM-LV with Linux 4.20Adam Ford
There have been a few fixes to the device trees, so this re-syncs the dts/dtsi files with Linux Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07ARM: DTS: Resync am3517-evm.dts with Linux 4.20Adam Ford
The DTS file for the AM3517 had the incorrect CD polarity. Resync with the fixed DTS file from Linux. Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07gpio: stm32f7: Move STM32_GPIOS_PER_BANK into gpio.hPatrice Chotard
To allow access to this define by other driver, move it into gpio.h Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07gpio: stm32f7: Add gpio bank holes managementPatrice Chotard
In some STM32 SoC packages, GPIO bank has not always 16 gpios. Several cases can occur, gpio hole can be located at the beginning, middle or end of the gpio bank or a combination of these 3 configurations. For that, gpio bindings offer the gpio-ranges DT property which described the gpio bank mapping. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07serial: bcm6858: remove driver and switch to bcm6345Álvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-07arm: implement {in, out}_{16, 32} and {clr, set, clrset}bits_{16, 32}Álvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-07arm: am335x-pdu001: Enable CONFIG_BLK and CONFIG_DM_MMCFelix Brack
This patch enables CONFIG_BLK as well as CONFIG_DM_MMC for the PDU001 board. It depends on Patrice Chotard's patch 'power: regulator: denied disable on always-on regulator' which prevents power cycling the vmmc supply. Without this patch the board will not boot as vmmc is unfortunately used by other board components, not just eMMC and micro SD card. Furthermore my patch 'dts: am335x-pdu001: Fix polarity of card detection input' is required to boot from external micro SD card. Without this patch no SD card will be detected and hence booting will fail. Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07dts: am335x-pdu001: Fix polarity of card detection inputFelix Brack
When a micro SD card is inserted in the PDU001 card cage, the card detection switch is opened and the corresponding GPIO input is driven by a pull-up. Hence change the active level of the card detection input from low to high. Signed-off-by: Felix Brack <fb@ltec.ch>
2018-12-07ARM: at91: lds: add test for SPL binary size and bss sizeEugen.Hristev@microchip.com
Add test for the SPL binary size and the bss section size. This will throw an error at build time if the SPL sections do not fit in the designated RAM area, thus avoiding oversizing the SPL. Based on original work by Wenyou Yang. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-12-06pinctrl: stm32: make pinctrl use hwspinlockBenjamin Gaignard
Protect configuration registers with a hardware spinlock. If a hwspinlock is defined in the device-tree node used it to be sure that none of the others processors on the SoC could change the configuration at the same time. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06hwspinlock: add stm32 hardware spinlock supportBenjamin Gaignard
Implement hardware spinlock support for STM32MP1. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8:fsl-layerscape: Add support for Chassis 3.2Priyanka Jain
NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: lsch3: Add support of serdes3 modulePriyanka Jain
Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: dts: fsl-ls2080a: add sata node supportPeng Ma
One ls2080a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: dts: fsl-ls1088a: add sata node supportPeng Ma
One ls1088a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: dts: fsl-ls1046a: add sata node supportPeng Ma
One ls1046a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: add support of MC framework for TFAPankit Garg
Add support of MC framework for TFA Make MC framework independent of boot source. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: sec_firmware: return job ring status as true in TFABOOTPankit Garg
Returns job ring status as true in TFABOOT, as one job ring is always reserved. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: sec_firmware: change el2_to_aarch32 SMC IDRajesh Bhagat
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17, it is applicable to both TFA and non-TFA boot. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: Update parsing boot sourceYork Sun
Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: skip OCRAM init for TFABOOTRajesh Bhagat
OCRAM initialization is performed by TFA, Hence skipped from u-boot. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: add SMC calls for DDR size and bank infoRajesh Bhagat
Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: bootcmd identification for TFABOOTPankit Garg
Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: remove EL3 specific erratas for TFABOOTRajesh Bhagat
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: identify boot source from PORSR registerRajesh Bhagat
PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: Add TFABOOT supportRajesh Bhagat
Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-12-06armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3Pankit Garg
Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: Enable routing SError exceptionYork Sun
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06rockchip: rk3399: Add Ficus EE board supportManivannan Sadhasivam
Add board support for Ficus EE board from Vamrs. This board utilizes common Rock960 family support. Following peripherals are tested and known to work: * Gigabit Ethernet * USB 2.0 * MMC Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> [Reworked based on common Rock960 family support] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-06rockchip: rk3399: Add Rock960 CE board supportManivannan Sadhasivam
Add board support for Rock960 CE board from Vamrs. This board utilizes common Rock960 family support. Following peripherals are tested and known to work: * USB 2.0 * MMC This commit also adds DDR configuration for LPDDR3-2GiB-1600MHz which is being used on the board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-06rockchip: rk3399: Add common Rock960 family from VamrsManivannan Sadhasivam
Rock960 is a family of boards based on Rockchip RK3399 SoC from Vamrs. It consists of Rock960 (Consumer Edition) and Ficus (Enterprise Edition) 96Boards. Below are some of the key differences between both Rock960 and Ficus boards: 1. Different host enable GPIO for USB 2. Different power and reset GPIO for PCI-E 3. No Ethernet port on Rock960 The common board support will be utilized by both boards. The device tree has been organized in such a way that only the properties which differ between both boards are placed in the board specific dts and the reset of the nodes are placed in common dtsi file. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [Added instructions for SD card boot] Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2018-12-06arm: dts: rockchip: add some common pin-settings to rk3399Randy Li
Those pins would be used by many boards. Commit grabbed from Linux: commit b41023282d07b61a53e2c9b9508912b1e7ce7b4f Author: Randy Li <ayaka@soulik.info> Date: Thu Jun 21 21:32:10 2018 +0800 arm64: dts: rockchip: add some common pin-settings to rk3399 Those pins would be used by many boards. Signed-off-by: Randy Li <ayaka@soulik.info> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Randy Li <ayaka@soulik.info> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-04move data structure out of cpu.hYork Sun
Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-04ARM: rmobile: Set environment variable containing CPU typeMarek Vasut
Set environment variable 'platform' containing the CPU type. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-04ARM: rmobile: Enable MMC extensionsMarek Vasut
Enable extended MMC commands and GPT partition table support. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> --- V2: Rebase on u-boot/master
2018-12-04ARM: dts: rmobile: Sync Gen3 DTs with Linux 4.19.6Marek Vasut
Synchronize DTs with mainline Linux 4.19.6 , commit 96db90800c06d3fe3fa08eb6222fe201286bb778 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> --- V2: Rebase on u-boot/master
2018-12-04ARM: dts: rmobile: Sync Gen2 DTs with Linux 4.19.6Marek Vasut
Synchronize DTs with mainline Linux 4.19.6 , commit 96db90800c06d3fe3fa08eb6222fe201286bb778 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> --- V2: Rebase on u-boot/master
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