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path: root/arch/powerpc/cpu/mpc85xx
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2013-08-09powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian
1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.hShaveta Leekha
It allows files not in the same path to use this function as required by B4 board file Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
2013-08-09powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIELiu Gang
When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF80000; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000", and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so the TLB entry will be from base address 0xffc00000 and with 4M size. Then the u-boot will set TLB entry 14 from base address "CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd00000. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff00000 with 1M size space. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09powerpc/mpc85xx: Workaround for A-005812York Sun
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09powerpc/mpc8xxx: Add memory reset controlYork Sun
JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09powerpc/corenet: Move RCW print to cpu.cYork Sun
The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09mpc85xx: Base emulator supportYork Sun
Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base. Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09powerpc/t4: Correct LIODN assignment for SRIOLiu Gang
For T4 platform, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-08-09powerpc/b4860: Correct LIODN assignment for SRIOLiu Gang
For B4, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-07-16powerpc/mpc85xx:Disable Debug TLB entry for non-minimal SPLPrabhakar Kushwaha
CONFIG_SPL_BUILD creates debug TLB entry, so disable it before init_tlbs. CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need of disable_tlb(). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/85xx: Add P1023RDB board supportChunhe Lan
P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/mpc85xx:Disable Debug TLB entry before init_tlbsPrabhakar Kushwaha
init_tlbs() initialize all the TLB entries required for the system. So disable DEBUG TLB entry before TLB entries initialization. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZEAxel Lin
If a variable is used as array subscript, it's valid value range is 0 ... ARRAY_SIZE -1. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/mpc85xx: modify the functionality clear_bss and aligning the end ↵Ying Zhang
address of the BSS There will clear the BSS in the function clear_bss(), the reset address of the BSS started from the __bss_start, and increased by four-byte increments, finally stoped depending on the address is equal to the _bss_end. If the end address __bss_end is not alignment to 4byte, it will be an infinite loop. 1. The reset action stoped depending on the reset address is greater than or equal the end address of the BSS. 2. The end address of the BSS should be 4byte aligned. Because the reset unit is 4 Bytes. This patch is on top of the patch "powerpc/mpc85xx: support application without resetvec segment in the linker script". Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/mpc85xx: support application without resetvec segment in the linker ↵Ying Zhang
script For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM, then jump to it to begin execution. After that, the SPL loads the final uboot image into DDR, then jump to it to begin execution. The segment .resetvec in the SPL and in final U-boot is useless. So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application. If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded and the segment .bootpg is placed in the previous 4K of the segment .text. Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/mpc85xx: work around erratum A-006593Scott Wood
Erratum A-006593 is "Atomic store may report failure but still allow the store data to be visible". The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit 21 to 1'b1. This may have a small impact on synthetic write bandwidth benchmarks but should have a negligible impact on real code." Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/boot: Change the macro of Boot from SRIO and PCIE master moduleLiu Gang
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc: Use lower case for the core namesFabio Estevam
Freescale documentation presents the PowerPC core names in lower case, such as "e300", "e500", "e600", etc. Change the upper case occurrences into lower case so that the core names reported in U-boot can match the ones from the documentation. While at it also fix a checkpatch error: ERROR: space prohibited before that close parenthesis ')' #53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81: + printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); Reported-by: Heinz Wrobel <heinz.wrobel@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/mpc85xx: new SPL support for IFC NANDPrabhakar Kushwaha
Linker script is not able find start.o binary. So add its absolute path in u-boot-spl.lds. This change is similar to u-boot-nand.lds common/Makefile: Avoid compiling unnecssary files fsl_ifc_spl.c : It is is responsible for reading u-boot binary from NAND flash and copying into DDR. It also transfer control from NAND SPL to u-boot image present in DDR. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399Prabhakar Kushwaha
IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or no NOR boot, do not compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_tMingkai Hu
To avoid sign extension problem, use explicit casting to cast the SDRAM size to type phys_size_t, or else, if the SDRAM size is 2G(0x80000000), it will be extended to 0xffffffff80000000 when phys_size_t is type 'unsigned long long'. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-2085xx: Change clock-frequency compatible to 2.0Andy Fleming
Accidentally applied an earlier version of the patch, which set the compatible to "fsl,qoriq-clockgen-2", lacking the final ".0". Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
2013-05-24powerpc/mpc85xx: Clear L1 D-cache lockYork Sun
dcbi instruction has been used to clear D-cache lock. However, the cache lock is persistent for e6500 core. Use dcblc to clear the lock explicitly. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24SECURE BOOT - Removed deletion of TLB entries codeRuchika Gupta
Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24powerpc/chassis2: Change core numbering schemeYork Sun
To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24powerpc/mpc8xxx: Add T1040 and variant SoCsYork Sun
T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24Add e6500 L2 replacement policy selectionJames Yang
This is compile-time config. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24powerpc/mpc85xx: check if core is disabled for showing statusYork Sun
"cpu <num> status" should check if core is disabled before printing the spin table location. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24Enable L2 cache parity/ECC error checkingJames Yang
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Update workaround for DDR erratum A-004934York Sun
The workaround has been updated to use a slightly different magic number. Change from 0x00003000 to 0x30003000. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.cRoy Zang
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/85xx: add missing QMAN frequency calculationShaohui Xie
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not be initialized, and QMAN will have a wrong frequency display. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Add T4160 SoCYork Sun
T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/t4240: Fix SerDes protocol arrays with const prefixYork Sun
Protocols are constants. Fix arrays with const prefix. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Fix PIR parsing for chassis2York Sun
The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/corenet2: Print SerDes protocol in decimalYork Sun
Use decimal and hexadecimal for protocol numbers. It helps to match with SoC user manual. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Fix portal setupYork Sun
Missing nodes of crypto, pme, etc in device tree is not a fatal error. Setting up the qman portal should skip the missing node and continue to finish the rest. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14T4/SerDes: correct the SATA indexRoy Zang
Lane H on SerDes4 should be SATA2 instead of SATA1 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14e6500: Move L1 enablement after L2 enablementAndy Fleming
The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/mpc85xx: Add definitions for HDBCR registersAndy Fleming
Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14powerpc/B4860: Corrected FMAN1 operating frequency print at u-bootSandeep Singh
The bit positions for FMAN1 freq in RCW is different for B4860. Also addded a case when FMAN1 frewuency is equal to systembus. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: Changed LIODN offset valuesCristian Sovaiala
Extending LIODN offset range from 1-5 to 1-10 While using a qman portal with a higher index the LIODN offset is incorrectly set, thus extending the range of offsets covers all 10 qman portals Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Acked-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/85xx: add SerDes bank 4 lanesTimur Tabi
Only some chips have four SerDes banks, so don't define lanes for a bank that doesn't exist. Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02mpc85xx: Fix a compiler warning when CONFIG_WATCHDOG is turned onHorst Kronstorfer
cpu.c:288:2: warning: implicit declaration of function 'reset_85xx_watchdog' [-Wimplicit-function-declaration] Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0)Xulei
On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen nodeTang Yuantian
For T4/B4, the clockgen node compatible string is updated to version 2. Add clock-frequency setting for this new version. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: add setting of clock-frequency for mpic nodeDongsheng.wang@freescale.com
Set the device tree property associated with the mpic source frequency. The frequency is used for mpic timer. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: Add revision properties in portal device tree node 'pme'Jeffrey Ladouceur
The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the pme portal node. This is required for software to determine which version of PME hardware is present and take appropriate actions. These properties are a direct reflection of the corresponding ccsr pme register value. Also removed unnecessary static global variables. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-04-01Consolidate bool typeYork Sun
'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
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