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path: root/arch/riscv/cpu/start.S
AgeCommit message (Expand)Author
2019-04-08riscv: hang if relocation of secondary harts failsLukas Auer
2019-04-08riscv: do not rely on hart ID passed by previous boot stageLukas Auer
2019-04-08riscv: add support for multi-hart systemsLukas Auer
2019-04-08riscv: save hart ID in register tp instead of s0Lukas Auer
2019-04-08riscv: delay initialization of caches and debug UARTLukas Auer
2018-12-18riscv: Save boot hart id to the global dataBin Meng
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng
2018-12-05riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen
2018-12-05riscv: Add kconfig option to run U-Boot in S-modeAnup Patel
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen
2018-11-26riscv: save hart ID and device tree passed by prior boot stageLukas Auer
2018-11-26riscv: do not blindly modify the mstatus CSRLukas Auer
2018-11-26riscv: remove unused labels in start.SLukas Auer
2018-11-26Drop CONFIG_INIT_CRITICALBin Meng
2018-11-26riscv: align mtvec on a 4-byte boundaryLukas Auer
2018-11-26riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer
2018-10-03riscv: Make start.S available for all targetsBin Meng