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path: root/arch/riscv/include/asm
AgeCommit message (Expand)Author
2020-04-23riscv: Provide a mechanism to fix DT for reserved memoryAtish Patra
2020-04-23riscv: Introduce SPL_SMP Kconfig option for U-Boot SPLBin Meng
2020-03-17riscv: Implement new SBI v0.2 extensionsBin Meng
2020-03-17riscv: Introduce a new config for SBI v0.1Bin Meng
2020-03-17riscv: Add SBI v0.2 extension definitionsBin Meng
2020-03-17riscv: Add basic support for SBI v0.2Bin Meng
2020-03-17riscv: Mark existing SBI as v0.1 SBIBin Meng
2020-03-17riscv: Fix sbi_remote_sfence_vma{,_asid}Bin Meng
2020-02-19dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>Masahiro Yamada
2020-02-19dma-mapping: fix the prototype of dma_unmap_single()Masahiro Yamada
2020-02-19dma-mapping: fix the prototype of dma_map_single()Masahiro Yamada
2020-01-25asm: dma-mapping.h: Fix dma mapping functionsVignesh Raghavendra
2019-12-10riscv: add option to wait for ack from secondary harts in smp functionsLukas Auer
2019-10-18gpio: sifive: add support for DM based gpio driver for FU540-SoCSagar Shrikant Kadam
2019-08-26riscv: add SPL supportLukas Auer
2019-08-26riscv: add run mode configuration for SPLLukas Auer
2019-08-15riscv: Access CSRs using CSR numbersBin Meng
2019-08-15riscv: Sync csr.h with Linux kernel v5.2Bin Meng
2019-08-11env: Drop environment.h header file where not neededSimon Glass
2019-05-09riscv: Introduce CONFIG_XIP to support booting from flashRick Chen
2019-04-08riscv: Add a SYSCON driver for Andestech's PLMTRick Chen
2019-04-08riscv: Add a SYSCON driver for Andestech's PLICRick Chen
2019-04-08riscv: add support for multi-hart systemsLukas Auer
2019-04-08riscv: import the supervisor binary interface header fileLukas Auer
2019-04-08riscv: add infrastructure for calling functions on other hartsLukas Auer
2019-02-27riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrdAnup Patel
2019-02-27riscv: Add place-holder asm/arch/clk.h for driver compilationAnup Patel
2019-02-27riscv: Add asm/dma-mapping.h for DMA mappingsAnup Patel
2018-12-18riscv: Save boot hart id to the global dataBin Meng
2018-12-18riscv: Add indirect stringification to csr_xxx opsBin Meng
2018-12-18riscv: Add exception codes for xcause registerBin Meng
2018-12-18riscv: Add CSR numbersBin Meng
2018-12-18riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng
2018-12-05riscv: Add kconfig option to run U-Boot in S-modeAnup Patel
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen
2018-11-26riscv: do not reimplement generic io functionsLukas Auer
2018-11-26riscv: make use of the barrier functions from LinuxLukas Auer
2018-11-26riscv: fix use of incorrectly sized variablesLukas Auer
2018-11-20Use _AC and UL macros from linux/const.hBaruch Siach
2018-10-03riscv: Remove CSR read/write defines in encoding.hBin Meng
2018-10-03riscv: Add a helper routine to print CPU informationBin Meng
2018-10-03riscv: Remove mach typeBin Meng
2018-10-03riscv: Remove setup.hBin Meng
2018-09-10arch: types.h: factor out fixed width typedefs to int-ll64.hMasahiro Yamada
2018-05-29riscv: cpu: nx25: Rename as ax25Rick Chen
2018-05-29SPDX: Convert single license tags to Linux Kernel styleRick Chen
2018-05-29riscv: Add board_quiesce_devices stubAlexander Graf
2018-05-29riscv: Add setjmp/longjmp codeAlexander Graf
2018-05-15riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()Bryan O'Donoghue
2018-05-15riscv: Define PLATFORM__SET_BIT for generic_set_bit()Bryan O'Donoghue