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AgeCommit message (Expand)Author
2019-08-26riscv: add a generic FIT generator scriptLukas Auer
2019-08-26riscv: support SPL stack and global data relocationLukas Auer
2019-08-26riscv: add SPL supportLukas Auer
2019-08-26riscv: add run mode configuration for SPLLukas Auer
2019-08-15riscv: Access CSRs using CSR numbersBin Meng
2019-08-15riscv: Sync csr.h with Linux kernel v5.2Bin Meng
2019-08-11env: Drop environment.h header file where not neededSimon Glass
2019-07-16efi_loader: use predefined constants in crt0_*_efi.SHeinrich Schuchardt
2019-06-05riscv: Add Microchip MPFS Icicle board supportPadmarao Begari
2019-05-18CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner
2019-05-18CONFIG_SYS_[DI]CACHE_OFF: convert to KconfigTrevor Woerner
2019-05-09RISCV: image: Add booti supportAtish Patra
2019-05-09riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen
2019-05-09riscv: Introduce CONFIG_XIP to support booting from flashRick Chen
2019-04-12dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong
2019-04-08riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failureRick Chen
2019-04-08riscv: dts: ae350 support SMPRick Chen
2019-04-08riscv: ax25: Andes specific cache shall only support in M-modeRick Chen
2019-04-08riscv: ax25: Add platform-specific Kconfig optionsRick Chen
2019-04-08riscv: Add a SYSCON driver for Andestech's PLMTRick Chen
2019-04-08riscv: Add a SYSCON driver for Andestech's PLICRick Chen
2019-04-08riscv: hang if relocation of secondary harts failsLukas Auer
2019-04-08riscv: do not rely on hart ID passed by previous boot stageLukas Auer
2019-04-08riscv: boot images passed to bootm on all hartsLukas Auer
2019-04-08riscv: add support for multi-hart systemsLukas Auer
2019-04-08riscv: save hart ID in register tp instead of s0Lukas Auer
2019-04-08riscv: delay initialization of caches and debug UARTLukas Auer
2019-04-08riscv: implement IPI platform functions using SBILukas Auer
2019-04-08riscv: import the supervisor binary interface header fileLukas Auer
2019-04-08riscv: add infrastructure for calling functions on other hartsLukas Auer
2019-02-27riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrdAnup Patel
2019-02-27riscv: Add SiFive FU540 board supportAnup Patel
2019-02-27riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel
2019-02-27riscv: Add place-holder asm/arch/clk.h for driver compilationAnup Patel
2019-02-27riscv: Add asm/dma-mapping.h for DMA mappingsAnup Patel
2019-02-27riscv: Rename cpu/qemu to cpu/genericAnup Patel
2019-01-15riscv: qemu: define standalone load addressLukas Auer
2019-01-15riscv: remove RISC-V standalone linker scriptLukas Auer
2019-01-15riscv: use invalidate/flush_*cache_range functions in cache.cLukas Auer
2019-01-15riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer
2019-01-15riscv: clarify error message on undefined exceptionsLukas Auer
2018-12-31riscv: bootm: Support booting VxWorksBin Meng
2018-12-18riscv: Remove ae350.dtsBin Meng
2018-12-18riscv: bootm: Change to use boot_hart from global dataBin Meng
2018-12-18riscv: Save boot hart id to the global dataBin Meng
2018-12-18riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng
2018-12-18riscv: Return to previous privilege level after trap handlingBin Meng
2018-12-18riscv: Fix context restore before returning from trap handlerBin Meng
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng