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AgeCommit message (Expand)Author
2018-12-18riscv: Save boot hart id to the global dataBin Meng
2018-12-18riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng
2018-12-18riscv: Return to previous privilege level after trap handlingBin Meng
2018-12-18riscv: Fix context restore before returning from trap handlerBin Meng
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng
2018-12-18riscv: Add indirect stringification to csr_xxx opsBin Meng
2018-12-18riscv: Update supports_extension() to use desc from cpu driverBin Meng
2018-12-18riscv: Add exception codes for xcause registerBin Meng
2018-12-18riscv: Add CSR numbersBin Meng
2018-12-18riscv: Remove non-DM version of print_cpuinfo()Bin Meng
2018-12-18riscv: Probe cpus during bootBin Meng
2018-12-18riscv: Enlarge the default SYS_MALLOC_F_LENBin Meng
2018-12-18riscv: qemu: Add platform-specific Kconfig optionsBin Meng
2018-12-18riscv: Implement riscv_get_time() API using rdtime instructionAnup Patel
2018-12-18riscv: Add a SYSCON driver for SiFive's Core Local InterruptorBin Meng
2018-12-18riscv: Introduce a Kconfig option for machine modeAnup Patel
2018-12-18riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng
2018-12-18riscv: qemu: Create a simple-bus driver for the soc nodeBin Meng
2018-12-18riscv: add Kconfig entries for the code modelLukas Auer
2018-12-05riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen
2018-12-05riscv: Add kconfig option to run U-Boot in S-modeAnup Patel
2018-12-02riscv: efi: Generate Microsoft PE format compliant imagesBin Meng
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen
2018-11-26riscv: dts: Add ae350_32.dts for RV32IRick Chen
2018-11-26riscv: dts: Sync to Linux Kernel ae350 dts.Rick Chen
2018-11-26riscv: align bootm implementation with that of other architecturesLukas Auer
2018-11-26riscv: save hart ID and device tree passed by prior boot stageLukas Auer
2018-11-26riscv: do not blindly modify the mstatus CSRLukas Auer
2018-11-26riscv: remove unused labels in start.SLukas Auer
2018-11-26Drop CONFIG_INIT_CRITICALBin Meng
2018-11-26riscv: align mtvec on a 4-byte boundaryLukas Auer
2018-11-26riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer
2018-11-26riscv: implement the invalidate_icache_* functionsLukas Auer
2018-11-26riscv: hang on unhandled exceptionsLukas Auer
2018-11-26riscv: treat undefined exception codes as reservedLukas Auer
2018-11-26riscv: complete the list of exception codesLukas Auer
2018-11-26riscv: do not reimplement generic io functionsLukas Auer
2018-11-26riscv: make use of the barrier functions from LinuxLukas Auer
2018-11-26riscv: fix use of incorrectly sized variablesLukas Auer
2018-11-26riscv: enable -fdata-sectionsLukas Auer
2018-11-26riscv: set -march and -mabi based on the Kconfig configurationLukas Auer
2018-11-26riscv: add Kconfig entries for the C and A ISA extensionsLukas Auer
2018-11-26riscv: select CONFIG_PHYS_64BIT on RV64I systemsLukas Auer
2018-11-26riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64ILukas Auer
2018-11-20Use _AC and UL macros from linux/const.hBaruch Siach
2018-11-18Kbuild: add LDFLAGS_STANDALONEDaniel Schwierzeck
2018-11-14riscv: bootm: Add dm_remove_devices_flags() call to do_bootm_linux()Bin Meng
2018-10-03riscv: allow native compilationHeinrich Schuchardt
2018-10-03riscv: cosmetic: Reword do_reset() printf message.Rick Chen