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2020-09-14riscv: define function set_gd()Heinrich Schuchardt
Function set_gd() is needed in the UEFI sub-system if the global data pointer is stored in a register. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-25cmd: provide command sbiHeinrich Schuchardt
Provide a command to display information about the SBI implementation. The output might look like: => sbi SBI 0.2 OpenSBI Extensions: sbi_set_timer sbi_console_putchar sbi_console_getchar sbi_clear_ipi sbi_send_ipi sbi_remote_fence_i sbi_remote_sfence_vma sbi_remote_sfence_vma_asid sbi_shutdown SBI Base Functionality Timer Extension IPI Extension RFENCE Extension Hart State Management Extension The command can be used to construct a unit test checking that the communication with the SEE is working. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com> Tested-by: Pragnesh Patel <pragnesh.patel@openfive.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com>
2020-08-25riscv: fix building with CONFIG_SPL_SMP=nHeinrich Schuchardt
Building with CONFIG_SPL_SMP=n results in: arch/riscv/lib/spl.c: In function ‘jump_to_image_no_args’: arch/riscv/lib/spl.c:33:6: error: unused variable ‘ret’ [-Werror=unused-variable] 33 | int ret; | ^~~ Define the variable ret as __maybe_unused. Fixes: 191636e44898 ("riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL") Fixes: 8c59f2023cc8 ("riscv: add SPL support") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-08-25riscv: fu540: Use correct API to get L2 cache controller base addressBin Meng
At present fdtdec_get_addr() is used to get L2 cache controller base address. This only works for a fixed #address-cells and #size-cells. Change to use fdtdec_get_addr_size_auto_parent() instead. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
2020-08-14riscv: additional crash informationHeinrich Schuchardt
If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14riscv: sifive: fu540: redundant initializationHeinrich Schuchardt
We should not initialize a variable if the value is overwritten before being read. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14riscv: remove redundant logical constraint.Heinrich Schuchardt
After if (ret) return ret; we know that ret is zero. Don't check it again. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-14riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC levelBin Meng
All FU540 driver related options should be in the SoC level Kconfig. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14riscv: sifive/fu540: spl: Rename soc_spl_init()Bin Meng
spl_soc_init() seems to be a better name, as all SPL functions names start from the spl_ prefix. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14riscv: Call spl_board_init_f() in the generic SPL board_init_f()Bin Meng
The generic SPL version of board_init_f() should give a call to board specific codes to initialize board in the SPL phase. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-04sifive: reset: add DM based reset driver for SiFive SoC'sSagar Shrikant Kadam
PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-08-04fu540: dtsi: add reset producer and consumer entriesSagar Shrikant Kadam
The resets to DDR and ethernet sub-system are connected to PRCI device reset control register, these reset signals are active low and are held low at power-up. Add these reset producer and consumer details needed by the reset driver. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-24riscv: dts: hifive-unleashed-a00: Make memory node available to SPLBin Meng
Make memory node available to SPL in prepration to updates to SiFive DDR RAM driver to read memory information from DT. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-24riscv: Fix linking error when building u-boot-spl with no SMP supportLeo Yu-Chi Liang
Switch off SMP support when building u-boot-spl would cause linking error as follow: undefined reference to 'secondary hart relocate' and 'smp_call_function'. Add macro to wrap up proper code region that needs SMP configuration on. Signed-off by: Leo Liang <ycliang@andestech.com> Cc: rick@andestech.com Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-24Revert "riscv: Allow use of reset drivers"Bin Meng
This reverts commit 958a3f464c7f8ef7e10db9feb663e9e80445ce2f. A more appropriate change below is already in mainline. Commit fd31e4fd184f ("riscv: Do not build reset.c if SYSRESET is on") Revert this patch, so that U-Boot can be built successfully for SiFive Fu540 board. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-07-24env: Enable SPI flash env for SiFive FU540Jagan Teki
SPI flash device on HiFive Unleashed has 32MiB Size. This patch adds SPI flash environment after U-Boot proper partition with a size of 128KiB. SPI flash partition layout(32MiB): 0 - 34 : reserved for GPT header 35 - 39 : unused 40 - 2087 : loader1 (SPL, FSBL) 2088 - 10279 : loader2 (U-Boot proper, U-Boot) 10280 - 10535 : environment 10536 - 65494 : rootfs 65528 - 65536 : distro script Note: the loader1 must start from 40th sector even though there are 6 free sectors prior since 40th sector is nearest flash sector boundary.  Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-24sifive: fu540: Add Booting from SPIJagan Teki
Add booting from SPI for SiFive Unleashed board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-24riscv: Make SiFive HiFive Unleashed board boot againBin Meng
Commit 40686c394e53 ("riscv: Clean up IPI initialization code") caused U-Boot failed to boot on SiFive HiFive Unleashed board. The codes inside arch_cpu_init_dm() may call U-Boot timer APIs before the call to riscv_init_ipi(). At that time the timer register base (e.g.: the SiFive CLINT device in this case) is unknown yet. It might be the name riscv_init_ipi() that misleads people to only consider it is related to IPI, but in fact the timer capability is provided by the same SiFive CLINT device that provides the IPI. Timer capability is needed for both UP and SMP. Considering that the original refactor does have benefits, that it makes the IPI code more similar to U-Boot initialization idioms. It also removes some quite ugly macros. Let's do the minimal revert instead of a complete revert, plus a fixes to arch_cpu_init_dm() to consider the SPL case. Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Leo Liang <ycliang@andestech.com>
2020-07-06Merge branch 'next'Tom Rini
Merge all outstanding changes from the current next branch in now that we have released.
2020-07-03riscv: use log functions in fdt_fixupHeinrich Schuchardt
Replace printf() and debug() by log_err() and log_debug(). "No reserved memory region found in source FDT\n" is not an error but a debug information. %s/can not/cannot/ - use the more common spelling. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-03riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel
Add L2 cache node to enable all cache ways from U-Boot proper. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-03riscv: Use optimized version of fdtdec_get_addr_size_no_parentAtish Patra
fdtdec_get_addr_size_no_parent is not an optimized version if parent node is already available with the caller. Use fdtdec_get_addr_size_auto_parent to read the "reg" property Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-03riscv: Do not return error if reserved node already existsAtish Patra
Not all errors are fatal. If a reserved memory node already exists in the destination device tree, we can continue to boot without failing. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-03riscv: Do not build reset.c if SYSRESET is onBin Meng
SYSRESET uclass driver already provides all the reset APIs, hence exclude our own ad-hoc reset.c implementation. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-02riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATEBin Meng
Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the reserved memory node for PMP protected memory regions. All RISC-V boards need to copy the reserved memory node from the device tree provided by the firmware to the device tree used by U-Boot. Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-02riscv: Expand the DT size before copy reserved memory nodeBin Meng
The FDT blob might not have sufficient space to hold a copy of reserved memory node. Expand it before the copy. Reported-by: Rick Chen <rick@andestech.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-02riscv: Avoid the reserved memory fixup if src and dst point to the same placeBin Meng
The copy of reserved memory node from source dtb to destination dtb can be avoided if they point to the same place. This is useful when OF_PRIOR_STAGE is used. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-02riscv: fu540: dts: Correct reg size of otp and dmc nodesBin Meng
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-02riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc nodeBin Meng
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-01riscv: dts: hifive-unleashed-a00: add cpu aliasesSagar Shrikant Kadam
Add cpu aliases to U-Boot specific dtsi for hifive-unleashed. Without aliases we see that the CPU device sequence numbers are set randomly and the cpu list/detail command will show it as follows: => cpu list 1: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 0: cpu@4 rv64imafdc Seems like CPU probing with dm-model also relies on aliases as observed in case spi. The fu540-c000-u-boot.dtsi has cpu nodes and so adding corresponding aliases we can ensure that cpu devices are assigned proper sequence as follows: => cpu list 1: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 4: cpu@4 rv64imafdc Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-01riscv: Add Sipeed Maix supportSean Anderson
The Sipeed Maix series is a collection of boards built around the RISC-V Kendryte K210 processor. This processor contains several peripherals to accelerate neural network processing and other "ai" tasks. This includes a "KPU" neural network processor, an audio processor supporting beamforming reception, and a digital video port supporting capture and output at VGA resolution. Other peripherals include 8M of sram (accessible with and without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; on-board usb-serial bridges; ports for cameras, displays, and sd cards; and ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly similar. Documentation for Maix boards is located at <http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is located at <https://kendryte.com/downloads/>. However, hardware details are rather lacking, so most technical reference has been taken from the standalone sdk located at <https://github.com/kendryte/kendryte-standalone-sdk>. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-07-01riscv: Add device tree for K210 and Sipeed Maix BitMSean Anderson
Where possible, I have tried to find compatible drivers based on the layout of registers. However, many devices remain untested. All untested devices have been left disabled, but some tentative properties (such as compatible strings, and clocks, interrupts, and resets properties) have been added. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-07-01riscv: Allow use of reset driversSean Anderson
Currently, one cannot use a reset driver on RISC-V. Follow the MIPS example, and disable the default reset handler when the sysreset driver is enabled. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-01riscv: Add option to support RISC-V privileged spec 1.9Sean Anderson
Some older processors (notably the Kendryte K210) use an older version of the RISC-V privileged specification. The primary changes between the old and new are in virtual memory, and in the merging of three separate counter enable CSRs. Using the new CSR on an old processor causes an illegal instruction exception. This patch adds an option to use the old CSRs instead of the new one. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-01riscv: Clean up IPI initialization codeSean Anderson
The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-01riscv: Clear pending interrupts before enabling IPIsSean Anderson
On some platforms (k210), the previous stage bootloader may have not cleared pending IPIs before transferring control to U-Boot. This can cause race conditions, as multiple harts all attempt to initialize the IPI controller at once. This patch clears IPIs before enabling them, ensuring that only one hart modifies shared memory at once. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-01riscv: Add headers for asm/global_data.hSean Anderson
This header depended on bd_t and ulong, but did not include the appropriate headers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-25bdinfo: riscv: Use generic bd_infoSimon Glass
At present riscv still uses its own private bd_info struct. Move it over to use the generic one like other archs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01Bin Meng
sbi_probe_extension() is an API defined in SBI v0.2, not v0.1. Fixes 7e249bc13aaf: ("riscv: Move all SMP related SBI calls to SBI_v01") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-06-04riscv: sbi: Remove sbi_spec_versionBin Meng
U-Boot defaults to use SBI v0.2. Howerver there is a global variable sbi_spec_version that stills refers to v0.1. Since it is not used anywhere, let's remove it. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-06-04riscv: sifive: fu540: add SPL configurationPragnesh Patel
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel
Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linuxPragnesh Patel
This sync has changes required to use GPIO in U-Boot and U-Boot SPL. Sync dts from linux v5.7-rc2 commit: "riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file" (sha1: 0a91330b2af9f71ceeeed483f92774182b58f6d9) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04riscv: sifive: dts: fu540: set ethernet clock ratePragnesh Patel
Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps, Earlier this is done by FSBL. With this change We can remove the ethernet clock rate code from FSBL. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04riscv: sifive: dts: fu540: add U-Boot dmc nodePragnesh Patel
Add dmc node to enable ddr driver. dmc is used to initialize the memory controller. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04sifive: dts: fu540: Add DDR controller and phy register settingsPragnesh Patel
Add DDR controller and phy register settings, taken from fsbl (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04riscv: sifive: dts: fu540: Add board -u-boot.dtsi filesPragnesh Patel
Devicetree files in FU540 platform is synced from Linux, like other platforms does. Apart from these U-Boot in FU540 would also require some U-Boot specific node like clint. So, create board specific -u-boot.dtsi files. This would help of maintain U-Boot specific changes separately without touching Linux dts(i) files which indeed easy for syncing from Linux between releases. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04riscv: Add _image_binary_end for SPLPragnesh Patel
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04riscv: sifive: fu540: Use OTP DM driver for serial environment variablePragnesh Patel
Use the OTP DM driver to set the serial environment variable. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-26riscv: Move all SMP related SBI calls to SBI_v01Atish Patra
SMP support for S-mode U-Boot is enabled only if SBI_V01 is enabled. There is no point in supporting SMP related (IPI and fences) SBI calls when SBI_V02 is enabled. Modify all the SMP related SBI calls to be defined only for SBI_V01. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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