Age | Commit message (Expand) | Author |
2015-04-18 | x86: chromebook_link: dts: Add PCH and LPC devices | Simon Glass |
2015-04-18 | dm: x86: pci: Convert chromebook_link to use driver model for pci | Simon Glass |
2015-04-16 | x86: Split up arch_cpu_init() | Simon Glass |
2015-04-16 | x86: Add a x86_ prefix to the x86-specific PCI functions | Simon Glass |
2015-01-13 | x86: ivybridge: Update microcode early in boot | Simon Glass |
2015-01-13 | x86: ivybridge: Drop support for ROM caching | Simon Glass |
2014-12-13 | x86: Add post failure codes for bist and car | Bin Meng |
2014-11-21 | x86: ivybridge: Add LAPIC support | Simon Glass |
2014-11-21 | x86: ivybridge: Add early init for PCH devices | Simon Glass |
2014-11-21 | x86: ivybridge: Perform Intel microcode update on boot | Simon Glass |
2014-11-21 | x86: ivybridge: Check BIST value on boot | Simon Glass |
2014-11-21 | x86: ivybridge: Perform initial CPU setup | Simon Glass |
2014-11-21 | x86: ivybridge: Add early LPC init so that serial works | Simon Glass |
2014-11-21 | x86: ivybridge: Enable PCI in early init | Simon Glass |
2014-11-21 | x86: chromebook_link: Implement CAR support (cache as RAM) | Simon Glass |
2014-11-21 | x86: Add chromebook_link board | Simon Glass |