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2019-10-08x86: cpu: Don't include the cpu driver in TPLSimon Glass
We don't need this driver very early in boot and it adds code size. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add a function to set variable MTRRsSimon Glass
Normally U-Boot handles MTRRs through an add/commit process which overwrites all MTRRs. But in very early boot it is not desirable to clear the existing MTRRs since they may be in use and it can cause a hang. Add a new mtrr_set_next_var() function which sets up the next available MTRR to the required region. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: pass 'type' to set_var_mtrr() in mtrr_set_next_var()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Refactor mtrr_commit() to allow for shared codeSimon Glass
Move the code that actually sets up the MTRR into another function so it can be used elsewhere in the file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add new common CPU functions for turbo/burst modeSimon Glass
Add a few more CPU functions that are common on Intel CPUs. Also add attribution for the code source. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist(); fix 2 typos in cpu_get_burst_mode_state() comments] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Tidy up some duplicate MSR definesSimon Glass
Some MSR registers are defined twice in different parts of the file. Move them together and remove the duplicates. Also drop some thermal defines which are not used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add common functions for TDP and perf controlSimon Glass
These functions are the same on modern Intel CPUs, so use common code to set them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: return false instead of 0 in cpu_ivybridge_config_tdp_levels(); fix 'muiltiplier' and 'desgn' typos] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Use a common bus clock for Intel CPUsSimon Glass
Modern Intel CPUs use a standard bus clock value of 100MHz, so put this in a common file and tidy up the copies. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add a common function to set CPU thermal targetSimon Glass
This code appears in a few places, so move it to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Use a common definition of MSR_IA32_PERF_CTLSimon Glass
Remove the duplicate definition as it is not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: pci: Drop the first parameter in pci_x86_r/w_config()Simon Glass
This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move acpi_s3.h to a common locationSimon Glass
At present this hedaer is only available on x86. To allow sandbox to use it for testing, move it to a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Rename turbo ratio MSR to MSR_TURBO_RATIO_LIMITSimon Glass
This MSR number is used on most modern Intel processors, so drop the confusing NHM prefix (which might mean Nehalem). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: drop MSR_IVT_TURBO_RATIO_LIMIT as no code uses it] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add more comments to the start-up codeSimon Glass
The full start-up sequence (TPL->SPL->U-Boot) can be a bit confusing since each phase has its own 'start' file. Add comments to explain this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Change condition for using CARSimon Glass
At present we assume that CAR (Cache-as-RAM) is used if HOBs (Hand-off blocks) are not, since HOBs typically indicate that an FSP is in use, and FSPs handle the CAR init. However this is a bit indirect, and for FSP2 machines which use their own CAR implementation (such as apollolake) but use the FSP for other functions, the logic is wrong. To fix this, add a dedicated Kconfig option to indicate when CAR is used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix a typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: fsp: Save usable RAM and hob_list in the handoff areaSimon Glass
The useable RAM is calculated when the RAM is inited. Save this value so that it can be easily used in U-Boot proper. Also save a pointer to the hob list so that it is accessible (before relocation only) in U-Boot proper. This avoids having to scan it in SPL, for everything U-Boot proper might need later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: guard handoff_arch_save() with IS_ENABLED(CONFIG_USE_HOB)] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: spl: Move broadwell-specific code out of generic x86 splSimon Glass
When TPL is running, broadwell needs to do different init from SPL. There is no need for this code to be in the generic x86 SPL file, so move it to arch_cpu_init(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: pci: Add a function to clear and set PCI config regsSimon Glass
At present the x86 pre-DM equivalent of pci_bus_clrset_config32() does not exist. Add it to simplify PCI init code on x86. Also add the missing functions to this header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add binman symbols to the imageSimon Glass
It is useful in SPL and TPL to access symbols from binman, such as the position and size of an entry in the ROM. Collect these symbols together in the SPL binaries. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move common Intel CPU info code into a functionSimon Glass
Add cpu_intel_get_info() to find out the CPU info on modern Intel CPUs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add parameter and return value descriptions] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Rename some FSP functions to have an fsp_ prefixSimon Glass
Given these exported function an fsp_ prefix since they are declared in an fsp.h header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Rename existing FSP code to fsp1Simon Glass
Since there is now a new version of the FSP and it is incompatible with the existing version, move the code into an fsp1 directory. This will allow us to put FSP v2 code into an fsp2 directory. Add a Kconfig which defines which version is in use. Some of the code in this new fsp1/ directory is generic across both FSPv1 and FSPv2. Future patches will address this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: tangier: Fix off-by-one error when preparing CSRTAndy Shevchenko
Intel iDMA 32-bit controller has 17 bits for the maximum block size value. Due to nature of the binary number representation the maximum value is 2^17 - 1. The original code misses the latter part in equation. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: tangier: Reserve PCI ECAM in motherboard resourcesAndy Shevchenko
Per PCI firmware specification the ACPI has to reserve the memory which is defined as PCI ECAM. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: show UEFI images involved in crashHeinrich Schuchardt
If a crash occurs, show the loaded UEFI images to facilitate analysis. This is an example output: => bootefi 0x1000000 Found 0 disks Hello world of bugs! Invalid Opcode (Undefined Opcode) EIP: 0010:[<06ceb06e>] EFLAGS: 00010206 Original EIP :[<fec9906e>] EAX: 00000000 EBX: 06cec000 ECX: 00000fd0 EDX: 00000001 ESI: 06ced18a EDI: 07d0fe10 EBP: 07fe27a0 ESP: 07d0fde0 DS: 0018 ES: 0018 FS: 0020 GS: 0018 SS: 0018 CR0: 00000033 CR2: 00000000 CR3: 00000000 CR4: 00000000 DR0: 00000000 DR1: 00000000 DR2: 00000000 DR3: 00000000 DR6: ffff0ff0 DR7: 00000400 Stack: 0x07d0fde8 : 0x00000000 0x07d0fde4 : 0x06ced040 --->0x07d0fde0 : 0x07fe27a0 0x07d0fddc : 0x00010206 0x07d0fdd8 : 0x00000010 0x07d0fdd4 : 0x06ceb06e UEFI image [0x06cea000:0x06cf0fff] pc=0x106e '/bug-i386.efi' ### ERROR ### Please RESET the board ### With the additional information provided by this patch we know that the problem occurred 0x106e after the load address of bug-i386.efi. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: qemu: Report high memory in the E820 tableBin Meng
Now that we are able to get the size of high memory from QEMU, report its memory range as usable ram. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: qemu: Support getting high memory sizeBin Meng
At present only size of memory that is below 4GiB is retrieved from QEMU. Add a function that gets size of memory that is above 4GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: qemu: Extract getting memory size to a separate routineBin Meng
This extracts getting memory size logic in dram_init() to a separate routine qemu_get_low_memory_size(). No functional changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-08-18x86: Remove x86 specific GD flags as they are not referenced at allStefan Roese
This patch removes the x86 architecture specific GD flags (GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S. But the coreboot target does not use start16.S at all and boots directly from the 32-bit start code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-11env: Rename environment.h to env_internal.hSimon Glass
This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-11env: Move TOTAL_MALLOC_LEN to environment.hSimon Glass
This declaration is only used in three files. Although it relates to malloc() it is actually only used during malloc() init. It uses CONFIG options including CONFIG_ENV_ADDR which are defined only in environment.h so this header must be included anyway, for TOTAL_MALLOC_LEN to be correct. Nove it to environment.h to simplify the common file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-09x86: slimbootloader: Set TSC information for tsc_timerPark, Aiden
Slim Bootloader already calibrated TSC and provides it to U-Boot. Therefore, U-Boot does not have to re-calibrate TSC. Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass TSC calibration and use the provided TSC frequency. - Get TSC frequency from performance info hob - Set tsc_base and clock_rate for tsc_timer driver Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: slimbootloader: Add serial driverPark, Aiden
Slim Bootloader provides serial port info thru its HOB list pointer. All these HOBs are eligible for Slim Bootloader based board only. - Get serial port information from the serial port info HOB - Leverage ns16550 driver with slimbootloader specific platform data Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: slimbootloader: Add memory configurationPark, Aiden
Slim Bootloader provides memory map info thru its HOB list pointer. Configure memory size and relocation memory from the HOB data, and provide e820 entries as well. - Get memory size from the memory map info HOB - Set available top memory lower than 4GB for U-Boot relocation - Provide e820 entries from the memory map info HOB Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: Add new slimbootloader CPU typePark, Aiden
This slimbootloader CPU type is to enable U-Boot as a payload which runs on top of Slim Bootloader (https://github.com/slimbootloader). The Slim Bootloader is designed with multi-stage architecture for the execution from reset vector to OS booting, and supports QEMU, Apollolake, Whiskeylake and Coffeelake platforms consuming Intel FSP (https://github.com/IntelFsp) for silicon initialization including CAR and memory initialization. The Slim Bootloader generates new HOB (Hand Off Block) which are serial port info, memory map info, performance data info and so on, and passes it to a Payload. U-Boot as a payload will use these HOB information for basic initialization such as serial console. As an initial commit, - Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type - Add new arch/x86/cpu/slimbootloader directory with minimum codes - Get hob_list pointer from Slim Bootloader Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: tangier: Populate CSRT for shared DMA controllerAndy Shevchenko
Intel Tangier has a shared DMA controller that, according to Microsoft spec, has to be presented in CSRT table. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-22watchdog: tangier: Convert to use WDT classAndy Shevchenko
Convert legacy driver to use watchdog class. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de>
2019-05-19x86: coreboot: make it possible to process unhandled tagsChristian Gmeiner
coreboot makes it possible to add own entries into coreboot's table at a per mainboard basis. As there might be some custom ones it makes sense to provide a way to process them. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-09Fix spelling of available.Vagrant Cascadian
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
2019-05-08x86: Add a way to jump from TPL to SPLSimon Glass
When TPL finishes it needs to jump to SPL with the stack set up correctly. Add a function to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Update PCH to work in TPLSimon Glass
The early init should only happen once. Update the probe method to deal with TPL, SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support TPL in Intel common codeSimon Glass
Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: ivybridge: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add common Intel code for SPLSimon Glass
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Select refcode and CPU code for SPLSimon Glass
Allow broadwell to build for SPL and include the reference code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Allow booting from SPLSimon Glass
At present broadwell only supports booting straight into U-Boot proper. Add a separate init file to boot from SPL into U-Boot proper, and select it when SPL is in use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Allow 16-bit init to be in TPLSimon Glass
At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add support for starting from SPL/TPLSimon Glass
When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Split CPU initSimon Glass
Split the CPU init into two parts - the 'full' init which happens in the first U-Boot phase, and the rest of the init that happens on subsequent stages. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Move init of debug UART to cpu.cSimon Glass
At present the debug UART is set up in sdram.c which is not the best place since it has nothing in particular to do with SDRAM. Since we want to support initing this in SPL too, move it to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: added 'broadwell' tag in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-25 13:44:29 +0000