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path: root/arch/x86/cpu
AgeCommit message (Expand)Author
2016-06-12x86: Probe pinctrl driver in cpu_init_r()Bin Meng
2016-05-30x86: baytrail: acpi: Fix I/O APIC ID in the MADT tableBin Meng
2016-05-30x86: quark: Generate ACPI FADT/MADT tablesBin Meng
2016-05-23x86: broadwell: Correct I/O APIC IDBin Meng
2016-05-23x86: quark: Assign a unique I/O APIC IDBin Meng
2016-05-23x86: Call lapic_setup() in interrupt_init()Bin Meng
2016-05-23x86: Remove SMP limitation in lapic_setup()Bin Meng
2016-05-23x86: Don't touch IA32_APIC_BASE MSR on Intel QuarkBin Meng
2016-05-23x86: Reserve configuration tables in high memoryBin Meng
2016-05-23x86: Unify reserve_arch() for all x86 boardsBin Meng
2016-05-23x86: Fix up PIRQ routing table checksum earlierBin Meng
2016-05-23x86: Call board_final_cleanup() in last_stage_init()Bin Meng
2016-05-23x86: qemu: rename qemu/acpi_table.cMiao Yan
2016-05-23cmd: qfw: bring ACPI generation code into qfw coreMiao Yan
2016-05-23cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan
2016-05-23x86: qemu: add comment about qfw register endiannessMiao Yan
2016-05-23x86: qemu: move x86 specific operations out of qfw coreMiao Yan
2016-05-23x86: qemu: split qfw command interface and qfw coreMiao Yan
2016-05-23cmd: qfw: remove qemu_fwcfg_free_files()Miao Yan
2016-05-23x86: qemu: fix ACPI Kconfig optionsMiao Yan
2016-05-23x86: qemu: Move qfw command over to cmd and add Kconfig entryTom Rini
2016-05-23x86: baytrail: Generate ACPI FADT/MADT tablesBin Meng
2016-05-23x86: irq: Enable SCI on IRQ9Bin Meng
2016-05-23x86: irq: Reserve IRQ9 for ACPI in PIC modeBin Meng
2016-05-23x86: Drop asm/acpi.hBin Meng
2016-05-17dm: Rename disk uclass to ahciSimon Glass
2016-04-22x86: Correct typo of Miao Yan's email addressBin Meng
2016-04-22x86: qemu: Drop our own ACPI implementationBin Meng
2016-03-22arm: x86: Drop command-line code when CONFIG_CMDLINE is disabledSimon Glass
2016-03-17x86: Support a chained-boot development flowSimon Glass
2016-03-17x86: ivybridge: Convert to use the common SDRAM codeSimon Glass
2016-03-17x86: Add common SDRAM-init codeSimon Glass
2016-03-17x86: Move common PCH code into a common placeSimon Glass
2016-03-17x86: Add a function to set the IOAPIC IDSimon Glass
2016-03-17x86: broadwell: Add support for high-speed I/O lane with MESimon Glass
2016-03-17x86: broadwell: Add support for SDRAM setupSimon Glass
2016-03-17x86: broadwell: Add power-control supportSimon Glass
2016-03-17x86: broadwell: Add reference code supportSimon Glass
2016-03-17x86: broadwell: Add an LPC driverSimon Glass
2016-03-17x86: broadwell: Add a northbridge driverSimon Glass
2016-03-17x86: broadwell: Add a SATA driverSimon Glass
2016-03-17x86: broadwell: Add a pinctrl driverSimon Glass
2016-03-17x86: broadwell: Add a PCH driverSimon Glass
2016-03-17x86: Add basic support for broadwellSimon Glass
2016-03-17x86: Update microcode for secondary CPUsSimon Glass
2016-03-17x86: ivybridge: Show microcode version for each coreSimon Glass
2016-03-17x86: Record the CPU details when starting each coreSimon Glass
2016-03-17x86: Move common MRC Kconfig options to the common fileSimon Glass
2016-03-17x86: Move Intel Management Engine code to a common placeSimon Glass
2016-03-17x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass