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2019-02-20sound: x86: Add beeping support in i8254Simon Glass
Adjust the code to allow beeping at different frequencies, using a calculated value for timer 2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20sound: x86: link: Add sound supportSimon Glass
Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: Adjust I/O macros to work on 64-bit machinesSimon Glass
At present these macros give warnings on 64-bit machines and do not correctly do 32-bit accesses. Update them to use linux types. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-13x86: do not use i386 code for x86_64 memory functionsHeinrich Schuchardt
arch/x86/lib/string.c contains assembler implementations of memcpy(), memmove(), and memset() written for i386. Don't use it on x86_64. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-12x86: tangier: Add initial ACPI support for PMIC deviceAndy Shevchenko
Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS and access is going via SCU device, enumerated via PCI. For now, we add just a minimum support of PMIC device to allow enabling, e.g. USB OTG, in the OS. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-10x86: acpi: Fix indentation in Intel Tangier ASL codeAndy Shevchenko
Make the indentation aligned with what used elsewhere in U-Boot. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-10x86: acpi: Enable RTC for Intel TangierAndy Shevchenko
Intel Tangier SoC has RTC inside. So, enable it in ACPI. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-05x86: acpi: Generate SPCR tableAndy Shevchenko
Microsoft specifies a SPCR (Serial Port Console Redirection Table) [1]. Let's provide it in U-Boot. [1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-05x86: acpi: Add SPCR table descriptionAndy Shevchenko
Add SPCR table description as it provided in Linux kernel. Port subtype for ACPI_DBG2_SERIAL_PORT is used as an interface type in SPCR. Thus, provide a set of definitions to be utilized later. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-14x86: Implement arch-specific io accessor routinesBin Meng
At present the generic io{read,write}{8,16,32} routines only support MMIO access. With architecture like x86 that has a separate IO space, these routines cannot be used to access I/O ports. Implement x86-specific version to support both PIO and MMIO access, so that drivers for multiple architectures can use these accessors without the need to know whether it's MMIO or PIO. These are ported from Linux kernel lib/iomap.c, with slight changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-06x86: acpi: Remove redundant Offset (0x00)Andy Shevchenko
New ACPI assembler issues a warning: board/intel/edison/dsdt.asl.tmp 13: Offset (0x00), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Indeed, in the OperationRegion the offset is 0x00 by default. Thus, drop unneeded Offset() use as suggested by ACPI assembler. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-28x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / regionStefan Roese
To allow bigger 64 bit prefetchable PCI regions in Linux, this patch changes the base address and range of the ACPI area passed to Linux. BayTrail can only physically access 36 bit of PCI address space. So just chaning the range without changing the base address won't work here, as 0xf.ffff.ffff is already the maximum address. With this patch, a maximum of 16 GiB of local DDR is supported. This should be enough for all BayTrail boards though. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-09x86: Update mtrr functions to allow leaving cache aloneSimon Glass
At present the mtrr functions disable the cache before making changes and enable it again afterwards. This is fine in U-Boot, but does not work if running in CAR (such as we are in SPL). Update the functions so that the caller can request that caches be left alone. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-17x86: tangier: acpi: add I2C6 nodeGeorgii Staroselskii
Now that we have I2C#6 working, it's time to add a corresponsing ACPI binding. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-17x86: cpu: introduce scu_ipc_raw_command()Georgii Staroselskii
This interface will be used to configure properly some pins on Merrifield that are shared with SCU. scu_ipc_raw_command() writes SPTR and DPTR registers before sending a command to SCU. This code has been ported from Linux work done by Andy Shevchenko. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-10arch: types.h: factor out fixed width typedefs to int-ll64.hMasahiro Yamada
All architectures have the same definition for s8/16/32/64 and u8/16/32/64. Factor out the duplicated code into <asm-generic/int-ll64.h>. BTW, Linux unified the kernel space definition into int-ll64.h a few years ago as you see in Linux commit 0c79a8e29b5f ("asm/types.h: Remove include/asm-generic/int-l64.h"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10Remove CONFIG_USE_STDINTMasahiro Yamada
You do not need to use the typedefs provided by compiler. Our compilers are either IPL32 or LP64. Hence, U-Boot can/should always use int-ll64.h typedefs like Linux kernel, whatever the typedefs the compiler internally uses. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-30x86: zimage: Remove acpi_rsdp_addr propagation to kernel boot parametersBin Meng
As of today, the proposal of adding "acpi_rsdp_addr" to the kernel boot protocol does not make its way to the kernel mainline. This creates some confusion if we leave it in the U-Boot code base. Remove it for now until we have a clear picture with kernel upstream. Note this eventually does a partial revert to commit 3469bf427454 ("x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-30x86: zimage: Support booting Linux kernel from an EFI payloadBin Meng
At present Linux kernel loaded from U-Boot as an EFI payload does not boot. This fills in kernel's boot params structure with the required critical EFI information like system table address and memory map stuff so that kernel can obtain essential data like runtime services and ACPI table to boot. With this patch, now U-Boot as an EFI payload becomes much more practical: it is another option of kernel bootloader, ie, can be a replacement for grub. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-25elf: Move x86 reloc defines to common elf.hAlexander Graf
We need to know about x86 relocation definitions even in cases where we don't officially build against the x86 target, such as with sandbox. So let's move the x86 definitions into the common elf header, where all other architectures already have them. Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-20x86: acpi: Prevent acpi_table.h from being included more than onceBin Meng
The wrapper #ifndef is currently missing in acpi_table.h. Add it to prevent it from being included multiple times. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-20x86: acpi: Move APIs unrelated to ACPI tables generation to a separate libraryBin Meng
acpi_find_fadt(), acpi_find_wakeup_vector() and enter_acpi_mode() are something unrelated to ACPI tables generation. Move these to a separate library. This also fixes several style issues reported by checkpatch in the original codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-20x86: Switch to use DM sysreset driverBin Meng
This converts all x86 boards over to DM sysreset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-02x86: Use microcode update from device tree for all processorsIvan Gorinov
Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies the microcode update data block encoded in Device Tree to the bootstrap processor but not passed to the other CPUs when multiprocessing is enabled. If the bootstrap processor successfully performs a microcode update from Device Tree, use the same data block for the other processors. Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed build errors on edison and qemu-x86] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-06-24x86: Change __kernel_size_t conditionals to use compiler provided definesBin Meng
Since commit bb0bb91cf0aa ("efi_stub: Use efi_uintn_t"), EFI x86 64-bit payload does not work anymore. The call to GetMemoryMap() in efi_stub.c fails with return code EFI_INVALID_PARAMETER. Since the payload itself is still 32-bit U-Boot, efi_uintn_t gets wrongly interpreted as int, but it should actually be long in a 64-bit EFI environment. This changes the x86 __kernel_size_t conditionals to use compiler provided defines instead. That way we always adhere to the build environment we're in and the definitions adjust automatically. Fixes: bb0bb91cf0aa ("efi_stub: Use efi_uintn_t") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-24x86: Add 64-bit setjmp/longjmp implementationIvan Gorinov
Add setjmp/longjmp functions for x86_64. Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-06-13x86: irq: Support discrete PIRQ routing registers via device treeBin Meng
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume consecutive PIRQ routing control registers. But this is not always the case on some platforms. Introduce a new device tree property intel,pirq-regmap to describe how the PIRQ routing register offset is mapped to the link number and adjust the irq router driver to utilize the mapping. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13x86: irq: Parse number of PIRQ links from device treeBin Meng
The "intel,pirq-link" property in Intel IRQ router's dt bindings has two cells, where the second one represents the number of PIRQ links on the platform. However current driver does not parse this information from device tree. This adds the codes to do the parse and save it for future use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13x86: irq: Change LINK_V2N and LINK_N2V to inline functionsBin Meng
LINK_V2N and LINK_N2V are currently defines, so they cannot handle complex logics. Change to inline functions for future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13x86: irq: Remove chipset specific irq router driversBin Meng
At present there are 3 irq router drivers. One is the common one and the other two are chipset specific for queensbay and quark. However these are really the same drivers as the core logic is the same. The two chipset specific drivers configure some registers that are outside the irq router block which should really be part of the chipset initialization. Now we remove these specific drivers and make all x86 boards use the common one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-03Define board_quiesce_devices() in a shared locationSimon Glass
This undocumented function relies on arch-specific code to declare a nop weak version. Add the weak function in common code instead to avoid having to duplicate the same function in each arch. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-15x86: Define PLATFORM__SET_BIT for generic_set_bit()Bryan O'Donoghue
x86 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT as a result generic_set_bit() is used instead of the architecturally provided __set_bit(). This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86 bitops.h will be called whenever generic_set_bit() is called - as opposed to the default cross-platform generic_set_bit(). Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2018-05-07SPDX: Convert all of our multiple license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-16x86: Rename e820entry to e820_entryBin Meng
This changes 'struct e820entry' to 'struct e820_entry' to conform with the coding style. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-04-16x86: Use 'unsigned int' in install_e820_map() functionsBin Meng
This fixes the following checkpatch warning: warning: Prefer 'unsigned int' to bare use of 'unsigned' Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-04-16x86: Update the io.h file to use {out|in}_{be|le}X macrosLukasz Majewski
The commit 3f70a6f57734 ("x86: Add clr/setbits functions") introduced the {read|write}_ macros to manipulate data. Those macros are not used by any code in the u-boot project (despite the io.h itself). Other architectures use io.h with {in|out}_* macros. This commit brings some unification across u-boot supported architectures. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-04-16x86: Add 64-bit memory-mapped I/O functionsIvan Gorinov
Add readq() and writeq() definitions for x86. Please note: in 32-bit code readq/writeq will generate two 32-bit memory access instructions instead of one atomic 64-bit operation. Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-03-30x86: zImage: Pass working device tree data to the kernelIvan Gorinov
On x86 platforms, U-Boot does not pass Device Tree data to the kernel. This prevents the kernel from using FDT loaded by U-Boot. Read the working FDT address from the "fdtaddr" environment variable and add a copy of the FDT data to the kernel setup_data list. Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add #include <linux/libfdt.h> to zimage.c to fix build error] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-30x86: acpi: Use an API to get the ACPI RSDP table addressBin Meng
At present the acpi_rsdp_addr variable is directly referenced in setup_zimage(). This changes to use an API for better encapsulation and extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-01-30x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parametersAndy Shevchenko
New field acpi_rsdp_addr, which has been introduced in boot protocol v2.14 [1], in boot parameters tells kernel the exact address of RDSP ACPI table. Knowing it increases robustness of the kernel by avoiding in some cases traversal through a part of physical memory. It will slightly reduce boot time by the same reason. [1] See Linux kernel commit 2f74cbf ("x86/boot: Add the ACPI RSDP address to struct setup_header::acpi_rdsp_addr") @ https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=2f74cbf for the details. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: updated the kernel commit git URL and fixed one style issue] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-30x86: tangier: Make _CRS for BTH0 Serialized to avoid warningAndy Shevchenko
ASL compiler warns: ASL board/intel/edison/dsdt.asl board/intel/edison/dsdt.asl.tmp 238: Method (_CRS, 0, NotSerialized) Remark 2120 - Control Method should be made Serialized ^ (due to creation of named objects within) Do as suggested by ASL compiler. Fixes: 5d8c4ebd95e2 ("x86: tangier: Add Bluetooth to ACPI table") Reported-by: Ferry Toth <fntoth@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-08x86: tangier: Add Bluetooth to ACPI tableAndy Shevchenko
As defined on reference board followed by Intel Edison a Bluetooth device is attached to HSU0, i.e. PCI 0000:04.1. Describe it in ACPI accordingly. Note, we use BCM2E95 ID here as one most suitable for such device based on the description in commit message of commit 89ab37b489d1 ("Bluetooth: hci_bcm: Add support for BCM2E95 and BCM2E96") in the Linux kernel source tree. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-08x86: tangier: Use actual GPIO hardware numbersAndy Shevchenko
The recent commit 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") in the Linux kernel reveals the issue we have in ACPI tables here, i.e. we must use hardware numbers for GPIO resources and, taking into consideration that GPIO and pin control are *different* IPs on Intel Tangier, we need to supply numbers properly. Besides that, it improves user experience since the official documentation for Intel Edison board is referring to GPIO hardware numbering scheme. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-12-21x86: tangier: Use official ACPI HID for FLIS IPAndy Shevchenko
FLIS IP since now gets its own ACPI ID. Drop PRP0001 workaround in favour of official ACPI HID. Corresponding kernel commit dabd4bc6de2b pinctrl: intel: merrifield: Introduce ACPI device table in the pin control subsystem tree [1] targeting v4.16. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=dabd4bc6de2b Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-10-27x86: acpi: Put sleepstates.asl to the common placeBin Meng
The supported sleep states are generic on Intel processors. Move the ASL definition to the common place. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-19x86: baytrail: fsp: Use a function to update the Azalia config pointerBin Meng
At present we directly pass the Azalia config pointer to the FSP UPD. This updates to use a function to do the stuff, like Braswell does. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19x86: fsp: Consolidate Azalia header fileBin Meng
So far there are two copies of Azalia struct defines with one in baytrail and the other one in braswell. This consolidates these two into one, put it in the common place, and remove the prefix pch_ to these structs to make their names more generic. This also corrects reset_wait_timer from us to ms. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-07x86: tangier: Enable ACPI support for Intel TangierAndy Shevchenko
Intel Tangier SoC is a part of Intel Merrifield platform which doesn't utilize ACPI by default. Here is an attempt to unleash ACPI flexibility power on Intel Merrifield based platforms. The change brings minimum support of the devices that found on Intel Merrifield based end user device. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-02x86: Use asm-generic/io.hPaul Burton
Convert the x86 architecture to make use of the new asm-generic/io.h to provide address mapping functions. As the generic implementations are suitable for x86 this is primarily a matter of moving code. This has only been build-tested, feedback from architecture maintainers is welcome. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>