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2016-03-17x86: Add an ICH6 pin configuration driverSimon Glass
Add a driver which sets up the pin configuration on x86 devices with an ICH6 (or later) Platform Controller Hub. The driver is not in the pinctrl uclass due to some oddities of the way x86 devices work: - The GPIO controller is not present in I/O space until it is set up - This is done by writing a register in the PCH - The PCH has a driver which itself uses PCI, another driver - The pinctrl uclass requires that a pinctrl device be available before any other device can be probed It would be possible to work around the limitations by: - Hard-coding the GPIO address rather than reading it from the PCH - Using special x86 PCI access to set the GPIO address in the PCH However it is not clear that this is better, since the pin configuration driver does not actually provide normal pin configuration services - it simply sets up all the pins statically when probed. While this remains the case, it seems better to use a syscon uclass instead. This can be probed whenever it is needed, without any limitations. Also add an 'invert' property to support inverting the input. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Update microcode for secondary CPUsSimon Glass
Each CPU needs to have its microcode loaded. Add support for this so that all CPUs will have the same version. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Support booting SeaBIOSBin Meng
SeaBIOS is an open source implementation of a 16-bit x86 BIOS. It can run in an emulator or natively on x86 hardware with the use of coreboot. With SeaBIOS's help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS. As U-Boot, we have to manually create a table where SeaBIOS gets system information (eg: E820) from. The table unfortunately has to follow the coreboot table format as SeaBIOS currently supports booting as a coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Implement functions for writing coreboot tableBin Meng
To prepare generating coreboot table from U-Boot, implement functions to handle the writing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Support writing configuration tables in high areaBin Meng
For those secondary bootloaders like SeaBIOS who want to live in the F segment, which conflicts the configuration table address, now we allow write_tables() to write the configuration tables in high area (malloc'ed memory). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Simplify codes in write_tables()Bin Meng
Given all table write routines have the same signature, we can simplify the codes by using a function table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Change write_acpi_tables() signature a little bitBin Meng
Change the parameter and return value of write_acpi_tables() to u32 to conform with other table write routines. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Use a macro for ROM table alignmentBin Meng
Define ROM_TABLE_ALIGN instead of using 1024 directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Change to use start/end address pair in write_tables()Bin Meng
Add a new variable rom_table_start and pass it to ROM table write routines. This reads better than previous single rom_table_end. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-14dm: Use uclass_first_device_err() where it is usefulSimon Glass
Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: fsp: Make sure HOB list is not overwritten by U-BootBin Meng
Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail. To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
2016-02-08Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini
2016-02-06Use correct spelling of "U-Boot"Bin Meng
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-05x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLEBin Meng
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c which is only built for legacy PCI. Also per checkpatch.pl warning, DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: irq: Move irq_router to a per driver privBin Meng
At present irq_router is declared as a static struct irq_router in arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense to move it to a per driver priv. Adjust existing APIs to accept an additional parameter of irq_router's udevice. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-28x86: qemu: add the ability to load and link ACPI tables from QEMUMiao Yan
This patch adds the ability to load and link ACPI tables provided by QEMU. QEMU tells guests how to load and patch ACPI tables through its fw_cfg interface, by adding a firmware file 'etc/table-loader'. Guests are supposed to parse this file and execute corresponding QEMU commands. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28x86: baytrail: Add option to disable the internal UART to setup_early_uart()Stefan Roese
This patch adds a parameter to the function setup_early_uart() to either enable or disable the internal BayTrail legacy UART. Since the name setup_early_uart() does not match its functionality any more, lets rename it to setup_internal_uart() as well in this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-24x86: Don't show an error when the MRC cache is up to dateSimon Glass
When the final MRC cache record is the same as the one we want to write, we skip writing since there is no point. This is normal behaviour. Avoiding printing an error when this happens. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24dm: x86: Add a northbridge uclassSimon Glass
Add a uclass for the northbridge / SDRAM controller found on some older Intel chipsets. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: Use the IRQ device when setting up the mptableSimon Glass
Instead of searching for the device tree node, use the IRQ device which has a record of it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24dm: Expand the uclass for Platform Controller Hubs (PCH)Simon Glass
A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19Add more SPDX-License-Identifier tagsTom Rini
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-14Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini
2016-01-13Fix board init code to respect the C runtime environmentAlbert ARIBAUD
board_init_f_mem() alters the C runtime environment's stack it is actually already using. This is not a valid behaviour within a C runtime environment. Split board_init_f_mem into C functions which do not alter their own stack and always behave properly with respect to their C runtime environment. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Thomas Chou <thomas@wytron.com.tw>
2016-01-13x86: fsp: Always use hex numbers in the hob command outputBin Meng
In the 'fsp hob' command output, decimal numbers and hexadecimal numbers are used mixedly. Now change to always use hex numbers to keep consistency. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-13x86: fsp: Set up init runtime buffer in update_fsp_configs()Bin Meng
fsp_init() runtime buffer parameter might be different across different platforms. Move this to update_fsp_configs(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13x86: fsp: Introduce CONFIG_FSP_USE_UPD Kconfig optionBin Meng
Not every FSP supports UPD, thus we introduce a Kconfig option CONFIG_FSP_USE_UPD and use it to wrap these common UPD handling codes in fsp_support.c. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13x86: fsp: Rename update_fsp_upd() and change its signatureBin Meng
To support platform-specific configurations (might not always be UPD on some platform), use a better name update_fsp_configs() and accepct struct fsp_config_data as its parameter so that platform codes can handle whatever configuration data for that FSP. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13x86: fsp: Rename shared_data to fsp_config_dataBin Meng
FSP has several config data like UPD, HDA verb table which can be overridden or provided by bootloader. Currently in U-Boot only UPD is handled via struct shared_data. To accommodate any platform, we rename shared_data to fsp_config_data and move the definition from common place fsp_support.h to platform-specific place fsp_configs.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13x86: fsp: Add boot_mode as a member of struct shared_dataBin Meng
Save boot_mode in struct shared_data for future refactoring. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13x86: fsp: Avoid cast stack_top in struct shared_dataBin Meng
Declare stack_top as u32 in struct shared_data and struct common_buf so that we can avoid casting in fsp_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13x86: fsp: Simplify fsp_continue()Bin Meng
There is no need to pass shared_data to fsp_continue() so we can remove unnecessary codes that simplifies the function a lot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-12dm: x86: pci: Adjust bios_run_on_x86() to use the DM PCI APISimon Glass
This function should take a struct udevice rather than pci_dev_t. Update it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12dm: Convert bios_interrupts to use DM PCI APISimon Glass
Adjust this code to use driver model for devices where possible. Since existing users have not been converted the old code must remain. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01x86: tsc: Move tsc_timer.c to drivers/timerBin Meng
To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01x86: tsc: Remove legacy timer codesBin Meng
Now that we have converted all x86 boards to use driver model timer, remove these legacy timer codes in the tsc driver. Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option, as it is not needed with driver model. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01x86: tsc: Add driver model timer supportBin Meng
This adds driver model timer support to x86 tsc timer driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01x86: tsc: Use notrace from <linux/compiler.h>Bin Meng
Replace __attribute__((no_instrument_function)) with notrace from <linux/compiler.h>. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13x86: Remove legacy pci codesBin Meng
Now that we have converted all x86 boards to use driver model pci, remove these legacy pci codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13x86: Rename pcat_ to i8254 and i8259 accordinglyBin Meng
Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c, to match their header file names (i8254.h and i8259.h). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13x86: Initialize i8254 timer counter 1Bin Meng
Initialize counter 1, used to refresh request signal. This is required for legacy purpose as some codes like vgabios utilizes counter 1 to provide delay functionality. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13x86: Fix cosmetic issues in the i8254 and i8259 codesBin Meng
This cleans up i8254 and i8259 codes to fix several cosmetic issues, like coding convention and some comments improvement. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13x86: Remove dead codes wrapped by PARANOID_IRQ_TRIGGERSBin Meng
PARANOID_IRQ_TRIGGERS is not referenced anywhere in U-Boot. Remove these dead codes wrapped by it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13x86: Rename CONFIG_SYS_NUM_IRQS to SYS_NUM_IRQSBin Meng
CONFIG_SYS_NUM_IRQS is actually not something we can configure, but an architecture defined number of ISA IRQs. Move it from x86-common.h to asm/interrupt.h and rename it to SYS_NUM_IRQS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21x86: fsp: Pass mrc cache to fsp_init() and save it to gd after fsp_init()Bin Meng
fsp_init() call has a parameter nvs_buf which is used by FSP as the MRC cache but currently is blindly set to NULL. Retreive the MRC cache from SPI flash and pass it to fsp_init() call. After the call, save FSP produced MRC cache to SPI flash too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21x86: Use struct mrc_region to describe a mrc regionBin Meng
Currently struct fmap_entry is used to describe a mrc region. However this structure contains some other fields that are not related to mrc cache and causes confusion. Besides, it does not include a base address field to store SPI flash's base address. Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to calculate the SPI flash base address, which unfortunately is not 100% correct as CONFIG_ROM_SIZE may not match the whole SPI flash size. Define a new struct mrc_region and use it instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21x86: Add more common routines to manipulate mrc cacheBin Meng
This adds mrccache_reserve(), mrccache_get_region() and mrccache_save() APIs to the mrccache codes. They are ported from the ivybridge implementation, but with some changes. For example, in the mrccache_reserve(), ivybridge version only reserves the pure MRC data, which causes additional malloc() when saving the cache as the save API needs some meta data. Now we change it to save the whole MRC date plus the meta data to elinimate the need for the malloc() later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21x86: Add various minor tidy-ups in mrccache codesBin Meng
Fix some nits, improve some comments and reorder some codes a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21x86: Do sanity test on the cache record in mrccache_update()Bin Meng
For the cache record to write in mrccache_update(), we should perform a sanity test to see if it is a valid one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21x86: Move mrccache.[c|h] to a common placeBin Meng
mrccache implementation can be common for all boards. Move it from ivybridge cpu directory to the common lib directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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