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AgeCommit message (Expand)Author
2014-11-25x86: Add Intel speedstep and turbo mode codeSimon Glass
2014-11-25x86: ivybridge: Set up XHCI USBSimon Glass
2014-11-25x86: ivybridge: Set up EHCI USBSimon Glass
2014-11-25x86: dts: Add SATA settings for linkSimon Glass
2014-11-25x86: ivybridge: Add SATA initSimon Glass
2014-11-25x86: dts: Add LPC settings for linkSimon Glass
2014-11-25x86: dts: Move PCI peripherals into a pci nodeSimon Glass
2014-11-25x86: ivybridge: Add additional LPC initSimon Glass
2014-11-25x86: ivybridge: Add PCH initSimon Glass
2014-11-25x86: Add a simple header file for ACPISimon Glass
2014-11-25x86: ivybridge: Add support for BD82x6x PCHSimon Glass
2014-11-25x86: Set up edge triggering on interrupt 9Simon Glass
2014-11-25x86: pci: Add handlers before and after a PCI hose scanSimon Glass
2014-11-25x86: Add ioapic.h headerSimon Glass
2014-11-25x86: Factor out common values in the link scriptSimon Glass
2014-11-25x86: Ensure that all relocation data is included in the imageSimon Glass
2014-11-25x86: Panic if there is no relocation dataSimon Glass
2014-11-25x86: Remove board_early_init_r()Simon Glass
2014-11-25x86: Add ivybridge directory to MakefileSimon Glass
2014-11-24Merge git://git.denx.de/u-boot-x86Tom Rini
2014-11-23x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada
2014-11-23kbuild: Descend into SOC directory from CPU directoryMasahiro Yamada
2014-11-23linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada
2014-11-21x86: Rename chromebook-x86 to corebootSimon Glass
2014-11-21x86: ivybridge: Implement SDRAM initSimon Glass
2014-11-21x86: ivybridge: Add LAPIC supportSimon Glass
2014-11-21x86: Make show_boot_progress() commonSimon Glass
2014-11-21x86: chromebook_link: Enable GPIO supportSimon Glass
2014-11-21x86: ivybridge: Add support for early GPIO initSimon Glass
2014-11-21x86: ivybridge: Add early init for PCH devicesSimon Glass
2014-11-21x86: dts: Add microcode updates for ivybridge CPUSimon Glass
2014-11-21x86: ivybridge: Perform Intel microcode update on bootSimon Glass
2014-11-21x86: ivybridge: Check BIST value on bootSimon Glass
2014-11-21x86: ivybridge: Perform initial CPU setupSimon Glass
2014-11-21x86: Add msr read/write functions that use a structureSimon Glass
2014-11-21x86: Add clr/setbits functionsSimon Glass
2014-11-21x86: Tidy up coreboot header usageSimon Glass
2014-11-21x86: ivybridge: Add early LPC init so that serial worksSimon Glass
2014-11-21x86: pci: Allow configuration before relocationSimon Glass
2014-11-21x86: ivybridge: Enable PCI in early initSimon Glass
2014-11-21x86: Support use of PCI before relocationSimon Glass
2014-11-21x86: Refactor PCI to permit alternate initSimon Glass
2014-11-21x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass
2014-11-21x86: Emit post codes in startup code for ChromebooksSimon Glass
2014-11-21x86: Build a .rom file which can be flashed to an x86 machineSimon Glass
2014-11-21x86: Add chromebook_link boardSimon Glass
2014-11-21x86: Allow timer calibration to work on ivybridgeSimon Glass
2014-11-21x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada
2014-11-21x86: Replace fill_processor_name() with cpu_get_name()Simon Glass
2014-11-21x86: Remove unnecessary find_fdt(), prepare_fdt() functionsSimon Glass