Age | Commit message (Expand) | Author |
2016-03-22 | arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled | Simon Glass |
2016-03-17 | x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support | Stefan Roese |
2016-03-17 | x86: Add support for the samus chromebook | Simon Glass |
2016-03-17 | x86: Support a chained-boot development flow | Simon Glass |
2016-03-17 | x86: dts: Drop memory SPD compatible string | Simon Glass |
2016-03-17 | x86: ivybridge: Convert to use the common SDRAM code | Simon Glass |
2016-03-17 | x86: Add common SDRAM-init code | Simon Glass |
2016-03-17 | x86: Move common PCH code into a common place | Simon Glass |
2016-03-17 | x86: Add a function to set the IOAPIC ID | Simon Glass |
2016-03-17 | x86: broadwell: Add support for high-speed I/O lane with ME | Simon Glass |
2016-03-17 | x86: broadwell: Add support for SDRAM setup | Simon Glass |
2016-03-17 | x86: broadwell: Add power-control support | Simon Glass |
2016-03-17 | x86: broadwell: Add reference code support | Simon Glass |
2016-03-17 | x86: broadwell: Add an LPC driver | Simon Glass |
2016-03-17 | x86: broadwell: Add a northbridge driver | Simon Glass |
2016-03-17 | x86: broadwell: Add a SATA driver | Simon Glass |
2016-03-17 | x86: broadwell: Add a pinctrl driver | Simon Glass |
2016-03-17 | x86: broadwell: Add a PCH driver | Simon Glass |
2016-03-17 | x86: Add basic support for broadwell | Simon Glass |
2016-03-17 | x86: Add support for running Intel reference code | Simon Glass |
2016-03-17 | x86: Drop all the old pin configuration code | Simon Glass |
2016-03-17 | x86: Add an ICH6 pin configuration driver | Simon Glass |
2016-03-17 | x86: link: Add pin configuration to the device tree | Simon Glass |
2016-03-17 | x86: Update microcode for secondary CPUs | Simon Glass |
2016-03-17 | x86: ivybridge: Show microcode version for each core | Simon Glass |
2016-03-17 | x86: Record the CPU details when starting each core | Simon Glass |
2016-03-17 | x86: Move common MRC Kconfig options to the common file | Simon Glass |
2016-03-17 | x86: Allow I/O functions to use pointers | Simon Glass |
2016-03-17 | x86: Add macros to clear and set I/O bits | Simon Glass |
2016-03-17 | x86: ivybridge: Drop sandybridge_early_init() | Simon Glass |
2016-03-17 | x86: Move Intel Management Engine code to a common place | Simon Glass |
2016-03-17 | x86: Rename PORT_RESET to IO_PORT_RESET | Simon Glass |
2016-03-17 | x86: Move common CPU code to its own place | Simon Glass |
2016-03-17 | x86: Move common LPC code to its own place | Simon Glass |
2016-03-17 | x86: Add the root-complex block to common intel registers | Simon Glass |
2016-03-17 | x86: Create a common header for Intel register access | Simon Glass |
2016-03-17 | x86: Move microcode code to a common location | Simon Glass |
2016-03-17 | x86: Move cache-as-RAM code into a common location | Simon Glass |
2016-03-17 | x86: cpu: Add functions to return the family and stepping | Simon Glass |
2016-03-17 | x86: broadwell: Add a few microcode files | Simon Glass |
2016-03-17 | x86: Add comments to the SIPI vector | Simon Glass |
2016-03-17 | x86: Tidy up mp_init to reduce duplication | Simon Glass |
2016-03-17 | x86: Correct duplicate POST values | Simon Glass |
2016-03-17 | x86: gpio: Correct GPIO setup ordering | Simon Glass |
2016-03-17 | x86: dts: link: Add board ID GPIOs | Simon Glass |
2016-03-17 | x86: dts: link: Move SPD info into the memory controller | Simon Glass |
2016-03-17 | x86: link: Add required GPIO properties | Simon Glass |
2016-03-17 | x86: Add some more common MSR indexes | Simon Glass |
2016-03-17 | x86: cpu: Make the vendor table const | Simon Glass |
2016-03-17 | x86: Support booting SeaBIOS | Bin Meng |