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2019-12-23arch: powerpc: add usb nodes to P5040 dtsRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23arch: powerpc: add usb nodes to T4240 dtsRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23arch: powerpc: add usb nodes to T104x dtsRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23powerpc: add usb nodes to T102x dtsRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23arch: powerpc: add usb nodes to P4080 dtsRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23arch: powerpc: add usb node to p2041 dtsRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23arch: powerpc: add usb node to p2020 dtsRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23arch: powerpc: add usb nodes to P1020 dtsRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23arch: powerpc: add usb node in p3041 dtsRan Wang
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-18Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 ↵Tom Rini
into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral
2019-12-17dm: i2c: EEPROM simulator add tests for addr offset maskRobert Beckett
Add support for setting the chip address offset mask to EEPROM sumulator and add tests to test it. Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17dm: i2c: EEPROM simulator allow tests visibility of addr and offsetRobert Beckett
Improve i2c EEPROM simulator testing by providing access functions to check the previous chip addr and offset. Given that we can now directly test the offsets, also simplified the offset mapping and allow for wrapping acceses. Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-15x86: Add chromebook_coralSimon Glass
Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add FSP supportSimon Glass
The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add FSP structuresSimon Glass
These are mostly specific to a particular SoC. Add the definitions for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add Kconfig and MakefileSimon Glass
Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add P2SB driverSimon Glass
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add SPL/TPL initSimon Glass
Add code to init the system both in TPL and SPL. Each phase has its own procedure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add a CPU driverSimon Glass
Add a bare-bones CPU driver so that CPUs can be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add SPL loadersSimon Glass
Add loaders for SPL and TPL so that the next stage can be loaded from memory-mapped SPI or, failing that, the Fast SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add PUNIT driverSimon Glass
Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a syscon driver since it only needs to be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add PCH driverSimon Glass
Add a driver for the Apollo Lake Platform Controller Hub. It does not have any functionality and is just a placeholder for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add LPC driverSimon Glass
This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add ITSS driverSimon Glass
This driver models some sort of interrupt thingy but there are so many abreviations that I cannot find out what it stands for. Possibly something to do with interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add hostbridge driverSimon Glass
This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add systemagent driverSimon Glass
This driver handles communication with the systemagent which needs to be told when U-Boot has completed its init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add pinctrl driverSimon Glass
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add UART driverSimon Glass
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device but also sets up the input clock with LPSS and supports configuration via of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add PMC driverSimon Glass
Add a driver for the Apollo Lake SoC. It supports the basic operations and can use device tree or of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: apl: Add basic IO addressesSimon Glass
Add some fixed IO and mmap addresses for use in the device tree and with some early-init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Move qemu CPU fixup function into its own fileSimon Glass
This function is specific to qemu so it seems best to keep it separate from the generic code. Move it out to a new file and update the condition to use if() instead of #ifdef Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add a generic Intel pinctrl driverSimon Glass
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add low-power subsystem (lpss) supportSimon Glass
This subsystem is present on various Intel SoCs. Add very basic support for taking an lpss device out of reset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Enable pinctrl in SPL and TPLSimon Glass
If these phases are used we typically want to enable pinctrl in then, so that pad setup and GPIO access are possible. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Make MSR_PKG_POWER_SKU commonSimon Glass
This is used on several boards so add it to the common file. Also add a useful power-limit value while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Separate out U-Boot and device tree in ROM imageSimon Glass
At present binman does not support updating a device tree that is part of U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get updated entry information. This makes binman_entry_find() work correctly. Do the same for SPL tool. In both cases, group the two parts into a section so that SPL symbols get the correct total size. It may be possible for binman to handle this automatically at some point, by ignoring u-boot.bin and always creating it from u-boot-nodtb.bin and u-boot.dtb Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Don't repeat microcode in U-Boot if not neededSimon Glass
At present if SPL sets up the microcode then it is still included in U-Boot as well. This is wasteful as microcode is large. Adjust the logic in the image to prevent this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add an fdtmap and image-headerSimon Glass
Add these entries to the ROM so that we can list the contents of an image with 'binman ls'. The image-header is not essential but does speed up access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add an option to control the position of SPLSimon Glass
For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different location from where SPL must be placed in ROM. In other words, although SPL runs before SDRAM is set up, it is not execute-in-place (XIP). Add a Kconfig option for the ROM position. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add an option to control the position of U-BootSimon Glass
The existing work-around for positioning U-Boot in the ROM when it actually runs from RAM still exists and there is not obvious way to change this. Add a proper Kconfig option to handle this case. This also adds a new bool property to indicate whether CONFIG_SYS_TEXT_BASE exists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Update .dtsi file for FSP2Simon Glass
Include the IFWI section and the FSP-M binary. The FSP-T binary is not currently used, as CAR is set up manually. Also drop the FSP binary as this relates only to FSP1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Disable microcode section for FSP2Simon Glass
At present we don't support loading microcode with FSP2. The correct way to do this is by adding it to the FIT. For now, disable including microcode in the image. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add support for newer CAR schemesSimon Glass
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add an option to include a FITSimon Glass
Many Intel SoCs require a FIT in order to boot properly. Add an option to include this and enable it by default. This term can be confused with FIT (Flat Image Tree) in U-Boot so the CONFIG option has to include 'X86'. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Don't include the BIOS emulator in TPLSimon Glass
We don't generally have enough space to run this, so don't build it into TPL. This helps reduce the size of TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Make the notify API call commonSimon Glass
The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new common API file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Allow remembering the location of FSP-SSimon Glass
FSP-S is used by the notify call after it has been used for silicon init. To avoid having to load it again, add a field to store the location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Set up an MTRR for the graphics frame bufferSimon Glass
The FSP-S may do this but at least for coral it does not. Set this up so that graphics is not deathly slow. It isn't clear whether the FSP is expected to set up MTRR. It is not mentioned in the APL FSP document. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Add FSP2 base supportSimon Glass
Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Correct wrong header inlude in fsp_support.cSimon Glass
This generic FSP file should include the generic FSP support header, not the FSP1 version. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>