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2011-10-05console: Implement pre-console bufferGraeme Russ
Allow redirection of console output prior to console initialisation to a temporary buffer. To enable this functionality, the board (or arch) must define: - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes) The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes Any earlier characters are silently dropped.
2011-10-04Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk
* 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/p3060: Add SoC related support for P3060 platform powerpc/85xx: Add support for setting up RAID engine liodns on P5020 powerpc/85xx: Refactor some defines out of corenet_ds.h fm-eth: Add ability for board code to disable a port powerpc/mpc8548: Add workaround for erratum NMG_LBC103 powerpc/mpc8548: Add workaround for erratum NMG_DDR120 powerpc/mpc85xxcds: Fix PCI speed powerpc/mpc8548cds: Fix booting message powerpc/p4080: Add support for secure boot flow powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards powerpc/p2041rdb: remove watch dog related codes powerpc/p2041rdb: updated description of cpld command powerpc/p2041rdb: add more ddr frequencies support powerpc/p2041rdb: set sysclk according to status of physical switch SW1 powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver powerpc/mpc8xxx: Add DDR2 to unified DDR driver powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps() powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en powerpc/85xx: Refactor P2041RDB to use common p_corenet files powerpc/85xx: refactor common P-Series CoreNet files for FSL boards powerpc/85xx: Enable CMD_REGINFO on corenet boards powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries powerpc/85xx: Fix USB protocol definitions for P1020RDB powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM powerpc/mpc8xxx: Move DDR RCW overriding to common code powerpc/mpc8xxx: Extend CWL table powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536 powerpc/85xx: Cleanup extern in corenet_ds board code powerpc/p2041rdb: Add ethernet support on P2041RDB board powerpc/85xx: Add networking support to P1023RDS powerpc/hydra: Add ethernet support on P5020/P3041 DS boards powerpc/85xx: Add FMan ethernet support to P4080DS powerpc/85xx: Add support for FMan ethernet in Independent mode powerpc/mpc8548cds: Cleanup mpc8548cds.c powerpc/mp: add support for discontiguous cores powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries fdt: Add new fdt_create_phandle helper fdt: Rename fdt_create_phandle to fdt_set_phandle powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010) powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC) fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010) powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB nand: Freescale Integrated Flash Controller NAND support powerpc/85xx: Add basic support for P1010RDB powerpc/85xx: Add support for new P102x/P2020 RDB style boards powerpc/85xx: relocate CCSR before creating the initial RAM area powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
2011-10-03powerpc/p3060: Add SoC related support for P3060 platformShengzhou Liu
Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/85xx: Add support for setting up RAID engine liodns on P5020Kumar Gala
Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/mpc8548: Add workaround for erratum NMG_LBC103Kumar Gala
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV]. Refer to the erratum LBIU3 of mpc8548. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/mpc8548: Add workaround for erratum NMG_DDR120Kumar Gala
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point. Signed-off-by: Gong Chen Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/p4080: Add support for secure boot flowRuchika Gupta
Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03microblaze: Clean up reset asm codeMichal Simek
- Remove code copying - Reset address is setup from first stage bootloader - Support reset vector setup on little endian Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-03microblaze: Save and restore first unused vectorMichal Simek
Use one memory space to detect little/big endian platforms. The first unused address(0x28) is used instead 0x0 address (reset vectors). Detection rewrited reset vector setup from first stage bootloader. Workflow: 1. Store 0x28 to r7 2. Do little/big endian test 3. Restore r7 to 0x28 Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-03microblaze: Setup MB vectors if feature is enable for u-bootMichal Simek
For example: Setup reset vectors if reset address is setup. Setup user exception vector if user exception is enabled Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-03microblaze: Remove debug saving valueMichal Simek
Forget to remove debug code. Signed-off-by: Michal Simek <monstr@monstr.eu>
2011-10-01sbc82xx: delete support for obsolete SBC8240/SBC8260Paul Gortmaker
The EST SBC8260 is over 10 years old, and the SBC8240 older than that. With the tiny amount of RAM (by today's standards), there really isn't anyone interested in running the latest U-boot on these EOL products anymore. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> CC: jon.diekema@smiths-aerospace.com
2011-10-01console: Squelch pre-console output in console functionsGraeme Russ
There are some locations in the code which anticipate printf() being called before the console is ready by squelching printf() on gd->have_console. Move this squelching into printf(), vprintf(), puts() and putc(). Also make tstc() and getc() return 0 if console is not yet initialised Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
2011-10-01Merge branch 'post' of git://git.denx.de/u-boot-blackfinWolfgang Denk
* 'post' of git://git.denx.de/u-boot-blackfin: Blackfin: uart: implement loop callback for post Blackfin: bf537-stamp/bf548-ezkit: update POST flash block range Blackfin: post: generalize led/button tests with GPIOs Blackfin: bf537-stamp: drop uart/flash post tests Blackfin: post: drop custom test list Blackfin: bf537-stamp: convert to gpio post hotkey
2011-09-30zmx25: Fix build warning due to 'get_reset_cause' defined but not usedFabio Estevam
When building the zmx25 target we get: Configuring for zmx25 board... generic.c:108: warning: 'get_reset_cause' defined but not used Fix this warning by defining get_reset_cause only if CONFIG_DISPLAY_CPUINFO is defined. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2011-09-30MX5: Clean up the output of "clocks" commandMarek Vasut
The new output looks like this: > clocks PLL1 800 MHz PLL2 665 MHz PLL3 216 MHz AHB 133000 kHz IPG 66500 kHz IPG PERCLK 665000 kHz Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
2011-09-30MX5: Add AHB clock reporting and fix IPG clock reportingMarek Vasut
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org>
2011-09-30MX5: Modify the PLL decoding algorithmMarek Vasut
The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Tested-by: Jason Liu <Jason.hui@linaro.org>
2011-09-30FEC: Move imx_get_mac_from_fuse() definition to fec_mxc.hMarek Vasut
Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
2011-09-30MX31: Disable watchdog during low-power modesFabio Estevam
Turn on the watchdog WDZST bit so that watchdog timer does not count during low power modes. Prior to applying this patch mx31pdk board got watchdog resets because when it booted in the Linux prompt and there was no activity, the system entered into idle mode while watchdog timer was still active. Fix this by disabling watchdog timer during idle mode. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30MX25: tx25: Avoid the usage of extern in C fileFabio Estevam
Avoid the usage of extern in C file as pointed out by checkpatch. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30MX31: Improve readability for reset causeFabio Estevam
Currently the reset cause is printed like: CPU: Freescale i.MX31 rev 2.0 at 531 MHz.Reset cause: POR Improve readability by adding a new line like it is done on other i.MX boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30ARM: mx25: Print the source of resetFabio Estevam
Print the source of reset during boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30ARM: mx25: Print the silicon revisonFabio Estevam
Print the silicon revison during boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30arm, davinci, da8xx: add cpuinfoHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci, am1808: add lowlevel functions for booting from NORHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci: add NOR Boot Configuration WordHeiko Schocher
to add the "NOR Boot Configuration Word" on AM18xx based boards, define CONFIG_SYS_DV_NOR_BOOT_CFG. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci: add ddr2 definitionHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci, am1808, gpio: add missing defines for bank 8Heiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci: add some missing defines in hardware.hHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci: add SYSCFG1 base and register structHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci: add RTC base addrHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci: add internal WDT support for AM1808 cpusHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci: add missing timer baseaddresses for !DA8xx cpuHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30arm, davinci: move davinci_timer in header fileHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30net, davinci_emac: add KSZ8864 switchHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30omap3: Fix compile warningSanjeev Premi
Building without option CONFIG_DISPLAY_CPUINFO leads to this warning: sys_info.c:50:14: warning: 'rev_s_37xx' defined but not used Signed-off-by: Sanjeev Premi <premi@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30mmc: omap: config VMMC, MMC1_PBIASBalaji T K
Config VMMC voltage to 3V for MMC/SD card slot and PBIAS settings needed for OMAP4 Fixes MMC/SD detection on boot from eMMC. Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30devkit8000: Fix build breakSandeep Paulraj
Found a build erros when i ran MAKEALL. So fix it. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30omap-common: reorganize spl.cSimon Schwarz
split-up spl.c into spl.c, spl_mmc.c and spl_nand.c. This avoids problems with missing defines if a board does not use mmc or nand. This includes adding spl_ prefix to some functions which are now public. spl_image_t is now a public type. Added some of the common functions to omap-common.h Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30omap3: implement boot parameter savingSimon Schwarz
Implements the saving of boot params passed by OMAP3 ROM code. Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30omap3: new SPL structure supportSimon Schwarz
Support for the new spl structure. Using the interface defined by Aneesh V for OMAP4 Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30omap-common: add nand spl supportSimon Schwarz
Add NAND support for the new SPL structure. Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30omap3: Configure RAM bank 0 if in SPLSimon Schwarz
OMAP3 relied on the memory config done by X-loader or Configuration Header. This has to be reworked for the implementation of a SPL. This patch configures RAM bank 0 if CONFIG_SPL_BUILD is set. Settings for Micron-RAM used by devkit8000 are added to mem.h Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30omap-common/omap4: relocate early UART clock setupSimon Schwarz
Moves the early UART clock setup setup_clocks_for_console() from preloader_console_init() to s_init() of OMAP4. This is done to prepare for OMAP3 integration. This patch was posted seperatly to the mailinglist but I decidet - since it is a prereqesit for this patch to add it. Former port to ML: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/104395 Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30OMAP3: Overo: Update GPMC timing for ethernet chipPhilip Balister
The existing timing does not quite meet the minimum requirements in the LAN9221 datasheet. The timing in this patch solves problems noticed on some parts. The patch also combines the CS configuration for the overo and igep0020 boards per request. Signed-off-by: Philip Balister <philip@opensdr.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-30Armada100: Enable Ethernet support for GplugDAjay Bhargav
This patch enables ethernet support for Marvell GplugD board. Network related commands works. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2011-09-30net: Adds Fast Ethernet Controller driver for Armada100Ajay Bhargav
This patch adds support for Fast Ethernet Controller driver for Armada100 series. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2011-09-30gpio: Add GPIO driver for Marvell SoC Armada100Ajay Bhargav
This patch adds support for generic GPIO driver framework for Marvell SoC Armada100. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
2011-09-29powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driverYork Sun
Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters. To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition. Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit (git 2.34.1) at 2024-12-26 18:57:17 +0000