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2018-12-19mips: jz47xx: Add JZ4780 SoC supportPaul Burton
Add initial support for the Ingenic JZ47xx MIPS SoC. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
2018-12-19mips: Add SPL headerPaul Burton
Add header with SPL boot mode and type definitions. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2018-12-19MSCC: add board support for the Luton based evaluation boardGregory CLEMENT
Adding the support for the Luton boards PCB91 which share common code with the Ocelots boards, including board code, device tree and configuration. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19MSCC: add board support for the Ocelots based evaluation boardsGregory CLEMENT
Adding the support for 2 boards sharing common code for Ocelot chip: PCB120 and PCB123 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19MSCC: add support for Luton SoCsGregory CLEMENT
As the Ocelots SoCs, this family of SoCs are found in the Microsemi Switches solution. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19MSCC: add support for Ocelot SoCsGregory CLEMENT
This family of SoCs are found in the Microsemi Switches solution and have already a support in the linux kernel. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19MIPS: Allow to prefetch and lock instructions into cacheGregory CLEMENT
This path add a new helper allowing to prefetch and lock instructions into cache. This is useful very early in the boot when no RAM is available yet. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19MIPS: move create_tlb() in an proper header: mipsregs.hGregory CLEMENT
Export create_tlb() as an inline function in mipsregs.h. It allows to remove the declaration of the function from the board files. Then it will allow also to use this function very early in the boot when the stack is not usable. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19MIPS: remove local_irq_[save|restore] from CP0 macrosDaniel Schwierzeck
With moving write_on_tlb() to arch/mips/include/asm/mipsregs.h there are now compiler warnings when some generic code includes asm/io.h. This happens for example when enabling OF live tree. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issuesStefan Roese
It has been noticed, that sometimes the d-cache is not in a "clean-state" when U-Boot is running on MT7688. This was detected when using the ethernet driver (which uses d-cache) and a TFTP command does not complete. Flushing the complete d-cache (again?) here seems to fix this issue. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19mips: xilfpga: fix DTC warningsDaniel Schwierzeck
This fixes following DTC warning: arch/mips/dts/nexys4ddr.dtb: Warning (compatible_is_string_list): /ethernet@10e00000/mdio/phy@1:compatible: property is not a string list As upstream DTS in Linux doesn't have the offending property, simply remove it to fix the warning. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19mips: ath79: fix DTC warningsDaniel Schwierzeck
Remove all interrupt nodes that cause warnings regarding a missing interrupt parent. There are no interrupt controller nodes defined and the device trees don't match the ones in Linux anymore. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19bmips: enable ar-5315u enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6318: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable vr-3032u enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm63268: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable dgnd3700v2 enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6362: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable ar-5387un enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6328: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable wap-5813n enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6368: add support for bcm6368-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable nb4-ser enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable hg556a enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6358: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable ct-5361 enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6348: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: enable f@st1704 enet supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6338: add support for bcm6348-enetÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6318: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm63268: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6362: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6328: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6368: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6358: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6348: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19bmips: bcm6338: add bcm6348-iudma supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-18riscv: Remove ae350.dtsBin Meng
This is not used by any board. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: bootm: Change to use boot_hart from global dataBin Meng
Avoid reading mhartid CSR directly, instead use the one we saved in the global data structure before. With this patch, BBL no longer needs to be hacked to provide the mhartid CSR emulation for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Save boot hart id to the global dataBin Meng
At present the hart id passed via a0 in the U-Boot entry is saved to s0 at the beginning but does not preserve later. Save it to the global data structure so that it can be used later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Adjust the _exit_trap() position to come before handle_trap()Bin Meng
With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Return to previous privilege level after trap handlingBin Meng
At present the trap handler returns to hardcoded M-mode/S-mode. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Fix context restore before returning from trap handlerBin Meng
sp cannot be loaded before restoring other registers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng
Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Do some basic architecture level cpu initializationBin Meng
In arch_cpu_init_dm() do some basic architecture level cpu initialization, like FPU enable, etc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add indirect stringification to csr_xxx opsBin Meng
With current csr_xxx ops, we cannot pass a macro to parameter 'csr', hence we need add another level to allow the parameter to be a macro itself, aka indirect stringification. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Update supports_extension() to use desc from cpu driverBin Meng
This updates supports_extension() implementation to use the desc string from the cpu driver whenever possible, which avoids the reading of misa CSR for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add exception codes for xcause registerBin Meng
This adds all exception codes in encoding.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Add CSR numbersBin Meng
The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18riscv: Remove non-DM version of print_cpuinfo()Bin Meng
With DM CPU driver, the non-DM version of print_cpuinfo() is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
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