| Age | Commit message (Collapse) | Author |
|---|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2020.04 (3rd)
- Enable ADMA and HS400 for the eMMC driver on 64-bit SoCs
- Add some convenient environment variables to handle SD card
- Sanitize the NAND controller reset sequence and its WP handling
- Sync DT with Linux
|
|
The compatible string "i2c-eeprom" is U-Boot own compatible, which
has never been approved by the DT community. "u-boot,i2c-offset-len"
is also a U-Boot own hack.
Linux adds "atmel,*" as generic compatibles, and U-Boot also followed
it by commit d7e28918aa3f ("i2c_eeprom: Add reading support").
The U-Boot own hack is no longer needed. Just sync with Linux.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
Import Linux commits:
37f3e0096f71 ("ARM: dts: uniphier: add reset-names to NAND controller node")
e98d5023fe1f ("arm64: dts: uniphier: add reset-names to NAND controller node")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
Import the nodename changes I made in Linux for avoiding dt-schama
warnings. This follows the $nodename patterns in the dt-schema.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
Commit f3729ba6e7b2 ("watchdog: mpc8xx_wdt: Watchdog driver and macros
cleanup") switched the watchdog to CONFIG_WATCHDOG. But this is not
compatible with the 8xx because it starts the watchdog HW timer at
reset and must be serviced from the very beginning including while
U-boot is executed in the firmware before relocation in RAM.
Select CONFIG_HW_WATCHDOG and make hw_watchdog_reset() visible.
Meanwhile, finalise the cleanup of arch/powerpc/cpu/mpc8xx/Kconfig by
removing the lines put in comment in that commit, and also remove
again the selection of CONFIG_MPC8xx_WATCHDOG which was removed by
that commit and brought back by mistake by commit b3134ffbd944
("watchdog: Kconfig: Sort entry alphabetically")
Note that there was an 'imply WATCHDOG' in the original commit but
it disappeared in the Kconfig alphabetical sorting, so no need to
remove it here.
Fixes: f3729ba6e7b2 ("watchdog: mpc8xx_wdt: Watchdog driver and macros cleanup")
Fixes: b3134ffbd944 ("watchdog: Kconfig: Sort entry alphabetically")
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Stefan Roese <sr@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
|
|
The base address 0x43f00000 is no longer true for the future SoC.
Extract the base address from the device tree.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
This workaround was previously needed for LD4, Pro4, sLD8, Pro5
SoCs. The boot ROM does not touch this register for PXs2/LD6b or
later.
Now that the reset signal of the Denali NAND controller is always
asserted in board_init() then deasserted in the driver, the
WRITE_PROTECT register gets back to the default value, which means
the write protect is deasserted.
This workaround can go away entirely.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
The comment /* deassert reset */ is wrong. It asserts the reset.
It no longer needs to stay in SPL. The NAND controller reset is
handled in the driver. So, this assert can be moved to the
board_init() of U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
Add handy macros:
- sdscript: source boot.scr in the file system of the SD media
- sdboot : boot the kernel using the images in the file system
of the SD media
- sdscript: update the boot firmware in the SD media
(in raw block sectors)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
- Update Sata node for T2080QDS and revert SATA related unrequired
patches.
|
|
Macro SZ_64K is undeclared. Include sizes.h to fix the compilation
error.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
The sata of our powerpc platforms are updated. These changes is to
fit the driver probe.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
|
This reverts commit 856b9cdb53f0e6c8d98f81cf71ef363c16b0aa0e.
Commit 856b9cdb53f0 ("powerpc: mpc85xx: delete FSL_SATA for T2080QDS
board.") is to fit support sata DM mode, Now the driver will be reverted,
So revert it.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rk3399: split roc-pc-rk3399 out of evb_rk3399
- sync dts from upstream kernel for rk3399,rk3288,px30
- boot_mode: find the saradc device name
|
|
To avoid "asm/dma-mapping.h: No such file or directory" error,
we need something.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
Put the target entries for rk3399 devices in alphabetical order.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.
Factor them out to <linux/dma-mapping.h>, and make all drivers to
include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>.
If we need to differentiate them for some architectures, we can
move the generic definitions to <asm-generic/dma-mapping.h>.
Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
dma_unmap_single() takes the dma address, not virtual address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
Make dma_map_single() return the dma address, and remove the
pointless volatile.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
indicate power mode
Added support for onboard LED's and push button. When powered board will be
in low power mode(yellow LED), on button press, board enters full power mode
(red LED) and boots u-boot.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
roc-pc-rk3399 board has one user button & three user LED's. Currently
we don't have any code support for these devices. Since button and LED's are
specific to roc-pc-rk3399 board, split it into its own board file and add code
support here.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
adc_channel_single_shot() requires the full device name e.g.
"saradc@ff100000", which differs between Rockchip SoC's, but they all
share the prefix "saradc"; find the ADC device with this name prefix and
use its full name.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
Sync rk3288-vyasa dts file from Linux.
This sync has changes required to work HDMI output on
Vyasa RK3288 board.
This sync excludes the io_domains node since it is not
available in rk3288.dtsi.
Changes like vcc50_hdmi, vdd10_lcd and ddc-i2c-bus are
not merged to Linux yet but wil resync later if any
further updates on this.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
Enable pre console buffer for rk3288 platform.
This would help to capture the console messages prior to
the console being initialised. Enabling this would help
to capture all the console messages on video output source
like HDMI. So we can find the full console messages of
U-Boot proper on HDMI display when enabled it for RK3288
platform boards.
Buffer address used for pre console is 0x0f000000 which is
ram base plus 240MiB. right now the Allwinner SoC is using
similar computation.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
There have been multiple peripherals added to the main px30 dtsi
in the Linux kernel since its addition to u-boot. So to make it easier
to sync board devicetrees, update the core dtsi from Linux.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
Move the U-Boot specific bits to a -u-boot.dtsi include so all the
u-boot.dtsi hierarchy is included.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
There's some bits in the U-Boot rk3399.dtsi that aren't yet in the
upstream Linux dtsi but are needed for early boot. This moves them
to the u-boot.dtsi to make it easier to sync the rest of rk3399.dtsi
with upstream.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
The upstream linux kernel for the Rockchip 3399 SoC use usbdrd3 naming so move
the two remaining devices over to that for their device trees to make it
easier to sync with upstream DTs.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
The core Rockchip spl code contains a default board_fit_config_name_match
implementation doing nothing. Individual boards may want to handle this
differently, so add a __weak atribute to make it possible to override
this function in other places.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
The script iterates over the given devicetrees and creates both
fdt_x node as well as a conf-node for each passed dt.
But there is a slight bug in that it always references fdt_1 in each
conf node instead of the matching fdt_x as expected.
So fix that by referencing the number of the current dt similar to
how the fdt_x nodes gets created.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme
|
|
Add support for Rev.Z of STM32MP15x cpu.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
|
|
Fix the following DT dtc warnings for stm32mp1 boards:
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@0:
node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@1:
node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@2:
node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@3:
node has a unit name, but no reg property
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
|
|
This patch fix the warning:
dt.dts: Warning (simple_bus_reg): Node /soc/ddr@5A003000
simple-bus unit address format error, expected "5a003000"
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
|
|
LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
cache the value at probe and pretend to use it later.
Keep the LTDC alone on PLL4_Q by moving the FDCAN to PLL4_R.
Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
|
|
Device tree and binding alignment with kernel v5.5-rc7
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
|
|
Update the driver to use the latest binding from kernel v5.5-rc1:
no more use syscon or regmap to access to pwr register and
only one pwr_regulators node with the compatibility "st,stm32mp1,pwr-reg"
is available.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
|
|
Device tree and binding alignment with kernel v5.4
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
|
|
Activate early console functionality on AM65x devices to allow for
early diagnostic messages until the main console is ready
to get activated.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
|
The boot parameter table index memory address for J721E was configured
to an incorrect value which prevented the use of this definition to
determine which boot parameter table is active which is needed to be
able to distinguish between primary and backup boot modes. Fix this
issue by updating the value to the correct one also in alignment with
the J721E Technical Reference Manual (TRM).
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
|
Data manual mentions the new silicon revisions as SR instead of PG. Use
the same nomenclature inside U-Boot as well.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
|
mcu uart will be used during uart boot for loading sysfw.itb. Since
sysfw is not yet available during uart load, power-domain cannot be
enabled. We need to rely on ROM for doing that, so disable power-domains
and clocks for mcu uart. Also fix the mcu uart frequency.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
|
Add scm_conf syscon node and its parents as well as the ethernet phy
node to u-boot.dtsi. This enables ethernet boot.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
|
Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier
board. This is an SoM with STM32MP15xx and an evaluation kit. The
baseboard provides Ethernet, UART, USB, CAN and optional display.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
|
|
First of all U-Boot is not that performance oriented as real run-time
software like OS or user bare-metal app so we may afford being not super
fast as we only being executed once. That in return allows us to be more
universal and support wider variety of devices.
And looking forward that will significantly reduce maintenance and simplify
support of newer architectures.
And while at it we add quad-word accessors like readq(), writeq() etc.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
|
|
It's a very rare if at all existing occasion when ARC CPU template
is used as is w/o any changes - in the end it's a beauty and competitive
advantage of ARC cores to be tailored for a particular use-case - and
so it doesn't make a lot of sense to offer template-based "-mcpu" selection.
Given for each and every platform we end-up adding quite a few more flags
it's logical to move "-mcpu" selection to platform's definition as well
which we exactly do here.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
|
|
Given now nsim_hs38 configuration is usable on QEMU and in QEMU
we have Virtio working perfectly fine the next logical step
is to add support of supported & known to work net & bkl to this
config.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
|
|
Since v2019.06 DesingWare nSIM supports DesignWare UART simulation
and so we may switch from pretty unusual ARC UART to much more standard
DesignWare UART (which in case of U-Boot is just an ordinary 16650 UART).
This among other things makes built dinaries compatible with our other
platforms to name a few: FPGA-based HAPS boards, QEMU and even ZeBU.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
|
|
sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
|
|
- Move P2SB from Apollo Lake to a more generic location
- Add a function to find a device by drvdata in DM core
- Enhancement of DM IRQ uclass driver
- Add a clock driver for Intel devices
- Add support for ACPI general-purpose events
- Add a TPM driver for H1/Cr50
- Enable TPM on Google Chromebook Coral
|
