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The existing ivybridge code predates the normal multi-core CPU init, and
it is not used. Remove it and add CPU nodes to the device tree so that all
four CPUs are set up. Also enable the 'cpu' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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This init can happen in the driver also. Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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The watchdog can be reset later when probing the LPC after relocation.
Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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We don't need to init the graphics controller so early. Move it alongside
the other graphics setup, just before we run the ROM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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We can drop the explicit probe of the PCH since the LPC is a child device
and this will happen automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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In preparation for adding an init() method to the LPC uclass, rename this
existing function so that it will not conflict.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Move more code into the northbridge probe() function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Add a driver with an empty probe function where we can move init code in
follow-on patches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Add a uclass for the northbridge / SDRAM controller found on some older
Intel chipsets.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Move SPI and port80 init to lpc_early_init(), called from the LPC's probe()
method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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There are no callers now. Platforms which need to set up interrupts their
own way can implement an interrupt driver. Drop this function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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Add a driver for interrupts on quark and move the code currently in
cpu_irq_init() into its probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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Instead of searching for the device tree node, use the IRQ device which has
a record of it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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Most x86 interrupt drivers will want to use the standard PIRQ routing and
table setup. Put this code in a common function so it can be used by those
drivers that want it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().
This removes the manual pirq_init() call. Where the platform does not have
an interrupt router defined in its device tree, no error is generated. Some
platforms do not have this.
Drop pirq_init() since it is no-longer used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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It seems likely that at some point we will want a generic interrupt uclass.
But this is a big undertaking as it involves unifying code across multiple
architectures.
As a first step, create a simple IRQ uclass and a driver for x86. This can
be generalised later as required.
Adjust pirq_init() to probe this driver, which has the effect of creating
routing tables and setting up the interrupt routing. This is a start
towards making interrupts fit better with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.
Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.
We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.
So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.
Thanks to Tom Cubie for sending me a board.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add the required pre-relocation tags and SDRAM init information for U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Bring in the current device tree files for rock2 from linux/next commit
719d6c1. Hopefully this is the latest one.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This has been added and we have references to it in the rock2 board. Add
this node.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Enable these devices using the VOPL video output device. We explicitly
disable VOPB in the device tree to avoid it taking over. Since this device
has an LCD display this comes up by default. If the display fails for some
reason then it will attempt to use HDMI. It is possible to force it to fail
(and thus fall back to HDMI) by puting 'return -EPERM' at the top of
rk_edp_probe(). For now there is no easy way to select between the two.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: Simon Glass <sjg@chromium.org>
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There is a minor error in the SDRAM timing. It does not seem to affect
anything so far. Fix it just in case.
Signed-off-by: Simon Glass <sjg@chromium.org>
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When the board does not use MMC SPL this code is a waste of space. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These work reasonable well, but there are a few errors:
- Brackets should be used to avoid unexpected side-effects
- When setting bits, the corresponding upper 16 bits should be set also
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Fix spaces in two comments in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a command that displays the PLLs and their current rate.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present the low-level init is skipped on rockchip. Among other things
this means that the instruction cache is left disabled. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.
Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These should match the datasheet naming. Adjust them.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a simple driver which implements the standard PWM uclass interface.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Turn on the EC and enable the keyboard.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The current method assumes that clocks are numbered from 0 and we can
determine a clock by its number. It is safer to use an ID in the clock's
platform data to avoid the situation where another clock is bound before
the one we expect.
Move the existing code into rk3036 since it still works there. Add a new
implementation for rk3288.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Use this function in preference to the macro.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Use this function in preference to the macro.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The current approach of using uclass_get_device() is error-prone. Another
clock (for example a fixed-clock) may cause it to break. Add a function that
does a proper search.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This hangs when activated (by probing the PMIC). Disable it for now until we
understand the root cause.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is defined in the device tree in Linux. Copy over the settings so that
this can be used instead of hard-coding the reset line.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is easier to deal with when using generic code since it allows us to
use a register index instead of naming each register.
Adjust it, adding an enum to improve readability.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This saves some code space in SPL which is useful on jerry.
Signed-off-by: Simon Glass <sjg@chromium.org>
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