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Ideally, the Linux kernel should get the hardware in its most
untouched state. For the most part, U-Boot does not reset the various
subsystems it touches before boot, and usually Linux deals with it, but
on some boards (cm_fx6) the Linux kernel fails to detect the ssd
correctly if sata is used by U-Boot.
Power off sata on OS boot so that Linux will have a clean state to work
with.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
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Add reset_sata() to the sata driver interface and implement it
for dwc_ahsata. This function cleans up after sata_init(), and
therefore accepts a device number like sata_init() does.
A dummy implementation is provided for the rest of the drivers.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
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Implement disable_sata_clock for mx6 SoCs.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
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Add imx6 thermal device to mx6 soc file. Read the cpu temperature
using this device to access onchip thermal sensor.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Add api to check and enable pll3 as required
for thermal sensor driver.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Move MX5 specific set_chipselect_size function into generic i.MX part,
such that MX6 based boards are able to use this function as well.
While doing this the iomuxc gpr member needed to be consolidated between
MX5 and MX6.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Many boards use a minimal .cfg file in the SPL case.
Introduce spl_sd.cfg so that we can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Commit 3ff46cc4 fixed exception vectors setting in
the general ARM case, by either copying the exception
and indirect vector tables to normal (0x00000000) or
high (0xFFFF0000) vectors address, or setting VBAR to
U-Boot's base if applicable.
i.MX27 SoC is ARM926E-JS, thus has only normal and
high options, but does not provide RAM at 0xFFFF0000
and has only ROM at 0x00000000; it is therefore not
possible to move or change its exception vectors.
Besides, i.MX27 ROM code does provide an indirect
vectors table but at a non-standard address and with
the reset and reserved vectors missing.
Turn the current vector relocation code into a weak
routine called after relocate_code from crt0, and add
strong version for i.MX27.
Series-Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Tested-by: Philippe Reynes <tremyfr@gmail.com>
Tested-by: Philippe Reynes <tremyfr@yahoo.fr>
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Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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mkimage -T mxs now support new flag in config file:
DISPLAYPROGRESS - makes boot process print HTLLC characters for each BootROM
instruction.
Signed-off-by: Alexey Ignatov <lexszero@gmail.com>
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The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display (optional, disabled by default)
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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The code for this board supports following features:
- Boot media support: NAND flash/SD card/SPI flash
- Support LCD display
- Support ethernet
- Support USB mass storage
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin
this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin
this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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add support for using spl code on at91sam9260 and at91sam9g45
based boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[adopt Bo's change in spl.c]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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- compile mpddrc ram init code also for AT91SAM9M10G45
based boards.
- in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
in the cr configuration
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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use the configure value for computing the ba_off value
not the value from the cr register. This leaded in a
wrong ram configuration on the upcoming corvus spl board
support.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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generate the boot.bin file for all atmel SoC (arm920, arm926, armv7)
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
[fix subject]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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The clock source for master clock can be slow clock, main clock,
plla clock or upll clock. So, make the clock source selection
field in mckr can be configured.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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We need to make sure the main clock ready field in MCFR is set
after switch to main crystal oscillator.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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This moves SH_32BIT to Kconfig, and removes SH_32BIT from config
files.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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The argument boot_flags of board_init_f() is not used at all in the
powerpc specific board.c init sequence. Now with the generic init
sequence, this boot_flags arg is used by board_init_f().
This patch sets the r3 register that is used to pass the boot_flags
argument from the start.S board_init_f() call to 0 prior to the function
call to avoid unknown content to end up in gd->flags.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.
So use IFC acessor functions instead of in_be32().
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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LIODN entry for B4860/B4420 mentions USB controller as "mph"
insread of "dr". This results in PAMU not permitting bus
transactions for USB DR controller on B4860 resulting in
USB function failure. Replacing "fsl-usb2-mph" with
"fsl-usb2-dr" allows USB DR controller bus transactions
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com>
Reviewed-by: Sun Yusong-R58495 <yorksun@freescale.com>
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NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some
platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure
on XAUI PHY, so set this bit definitely to align with the RM.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0xffff if clause 22 is used to read 10G phy_id;
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-By: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Add initial support for TBS2910 Matrix ARM miniPC.
Support includes MMC, Ethernet, UARTs, HDMI, USB, SATA, PCI, I2C, RTC.
Signed-off-by: Soeren Moch <smoch@web.de>
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Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Stefano Babic <sbabic@denx.de>
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add SUPPORT_SPL feature for iMX6 SabreSD. It need to use
mx6sabresd_spl_defconfig to compile it.
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
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Add two missing Kconfig options for Novena and drop the SPL
from the Novena config.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
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Add support for the 2 ehci controllers found on the sun6i (A31) soc.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Marek Vasut <marex@denx.de>
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Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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In preparation for adding sun6i dram support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Not used atm, for future use (e.g. PSCI).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).
Also add some extra clock register constant defines.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs)
collected the default values of CONFIG_SYS_CPU into arch/arm/Kconfig.
This commit moves "armv8" to there for consistency.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Georges Savoundararadj <savoundg@gmail.com>
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This commit adds "select CPU_V7" for some new boards that were not
covered by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).
Redundant "SYS_CPU" defines and "string" directives should be removed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Georges Savoundararadj <savoundg@gmail.com>
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There is no board with CPU "arm_intcm".
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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Precisely, these boards are SH4A rather than SH4.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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