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2019-11-03x86: Add a CPU init function for TPLSimon Glass
For TPL we only need to set up the features and identify the CPU to a basic level. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: tpl: Add a fake PCI busSimon Glass
In TPL we try to minimise code size so do not include the PCI subsystem. We can use fixed BARs and drivers can directly program the devices that they need. However we do need to bind the devices on the PCI bus and without PCI this does not ordinarily happen. As a work-around, define a fake PCI bus which does this binding, but no other PCI operations. This is a convenient way to ensure that we can use the same device tree for TPL, SPL and U-Boot proper: TPL - CONFIG_TPL_PCI is not set (no auto-config, fake PCI bus) SPL - CONFIG_SPL_PCI is set (no auto-config but with real PCI bus) U-Boot - CONFIG_PCI is set (full auto-config after relocation) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: spl: Support init of a PUNITSimon Glass
The x86 power unit handles power management. Support initing this device which is modelled as a new type of system controller since there are no operations needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: timer: Use a separate flag for whether timer is initedSimon Glass
At present the value of the timer base is used to determine whether the timer has been set up or not. It is true that the timer is essentially never exactly 0 when it is read. However 'time 0' may indicate the time that the machine was reset so it is useful to be able to denote that. Update the code to use a separate flag instead. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-01Merge tag 'dm-pull-29oct19' of git://git.denx.de/u-boot-dmTom Rini
- Fix for patman with email addresses containing commas - Bootstage improvements for TPL, SPL - Various sandbox and dm improvements and fixes
2019-10-31lib: time: Add microsecond timerMarek Vasut
Add get_timer_us(), which is useful e.g. when we need higher precision timestamps. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> [trini: Fixup arch/arm/mach-bcm283x/include/mach/timer.h] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-10-30Merge tag 'u-boot-clk-23Oct2019' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-clk - Add I2C clocks for i.MX6Q CCF driver - Fix check in clk_set_default_parents() - Managed API to get clock from device tree - Fixes for core clock code (including sandbox regression tests)
2019-10-30Merge branch '2019-10-28-azure-ci-support'Tom Rini
- Clean up Travis-CI slightly and then add support for Microsoft Azure pipelines, all from Bin Meng.
2019-10-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
- H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil)
2019-10-29arm: mvebu: Avoid generating kwbimage.cfg in the source treeBin Meng
At present some boards generate kwbimage.cfg in the source tree during the build. This breaks buildman testing on some systems where the source tree is read-only. Update makefile rules to generate it in the build tree instead. Note some other boards have the kwbimage.cfg file written in advance, hence we need check if the file exists in the build tree first, otherwise we fall back to one in the source tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-27sandbox: test: Add a prototype for sandbox_set_enable_memio()Simon Glass
This function needs a prototype so that tests can use it. Add one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-27sandbox: Drop 'const' from sandbox_write()Simon Glass
This function writes to its address so the address should not be declared as const. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-25Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsTom Rini
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
2019-10-25Merge branch '2019-10-24-ti-imports'Tom Rini
- Enable DFU on dra7xx boards - Further Keystone 3 platform improvements
2019-10-25arm: dts: k3-am65: Add R5F ranges in interconnect nodesSuman Anna
Add the address spaces for the R5F cores in MCU domain to the ranges property of the cbass_mcu interconnect node so that the addresses within the R5F nodes can be translated properly by the relevant OF address API. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25armv7R: K3: j721e: Add support for triggering ddr init from SPLLokesh Vutla
In SPL, DDR should be made available by the end of board_init_f() so that apis in board_init_r() can use ddr. Adding support for triggering DDR initialization from board_init_f(). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25arm: dts: k3-j721e: Add ddr nodeLokesh Vutla
Use the 3733MTs DDR configuration that is auto generated from DDR_Regconfig tool. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2019-10-25ram: k3-am654: Do not rely on default values for certain DDR registerJames Doublesin
Added the following registers to the DDR configuration: - ACIOCR0, - ACIOCR3, - V2H_CTL_REG, - DX8SLxDQSCTL. Modified enable_dqs_pd and disable_dqs_pd to only touch the associated bit fields for pullup and pulldown registers (to preserve slew rate and other bits in that same register). Also update the dts files in the same patch to maintain git bisectability. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25armv7r: dts: am654-base-board: Rename 1600MHz to 1600MTs in dtsi filenameJames Doublesin
The current configuration of DDR on AM654 base board is for 1600MTs but the file name is specified as k3-am654-base-board-ddr4-1600MHz.dtsi. Since 1600MHz is misleading, rename it to k3-am654-base-board-ddr4-1600MTs.dtsi Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25arm: K3: Clean and invalidate Linux Image before jumping to LinuxLokesh Vutla
U-Boot cleans and invalidate L1 and L2 caches before jumping to Linux by set/way in cleanup_before_linux(). Additionally there is a custom hook provided to clean and invalidate L3 cache. Unfortunately on K3 devices(having a coherent architecture), there is no easy way to quickly clean all the cache lines for L3. The entire address range needs to be cleaned and invalidated by Virtual Address. This can be implemented using the L3 custom hook but it take lot of time to clean the entire address range. In the interest of boot time this might not be a viable solution. The best hit is to make sure the loaded Linux image is flushed so that the entire image is written to DDR from L3. When Linux starts running with caches disabled the full image is available from DDR. Reported-by: Andrew F. Davis <afd@ti.com> Reported-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25boot: arm: Enable support for custom board_prep_linuxLokesh Vutla
Once the arch specific boot_prepare_linux completes, boards wants to have a custom preparation for linux. Add support for a custom board_prep_linux. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25ARM: dts: dra7: Add usb peripheral nodes in splFaiz Abbas
Add usb peripheral and usb phy nodes in spl to enable SPL_DFU bootmode. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-25Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
- DWC3 improvements - i.MX7 EHCI bugfix
2019-10-25Merge tag 'u-boot-atmel-2020.01-b' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features and fixes for 2020.01 cycle This feature set includes Eugen's work on a new tiny flexcom driver and eeprom mac retrieval for the sam9x60-ek board.
2019-10-25Merge tag 'xilinx-for-v2020.01-part2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 part 2 common: - Fix manual relocation for repeatable commands arm: - Also clean up generated dtbos microblaze: - Add support for Manual relocation in crypto framework - Tune and align architecture bootm support zynq: - DT sync ups - Some defconfig updates - Remove empty board_early_init_f() zynqmp: - Clean firmware handing via drivers/firmware/ - DT/defconfig name alignments - DT cleanups with using firmware based clock driver - Some defconfig updates - Add IIO ina226 DT description - Tune zynqmp_psu_init_minimalize.sh script - Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216 versal: - Clean firmware handing via drivers/firmware/ - Add gpio support - Enable DT overlay/USB/CLK/FPGA - DT updates - Tune mini configuration spi: - gqspi - Remove unused headers
2019-10-25mips: mtmips: select essential drivers in KconfigWeijie Gao
Some drivers (clk, pinctrl, reset, ...) are necessary for reset of the system, they should be always selected. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add default pinctrl to eth nodes for all boardsWeijie Gao
This patch adds default eth pinctrl for all boards. There are two pinctrl nodes used for two scenarios: ephy_iot_mode - for IOT boards which have only one port (PHY0) ephy_router_mode - For routers which have more than one ports Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add default pinctrl for gardena-smart-gateway-mt7688Weijie Gao
This adds default pinctrl (dual SPI chip select) for gardena smart gateway Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add mmc related nodes for mt7628an.dtsiWeijie Gao
This patch adds mmc related nodes for mt7628an.dtsi Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: enable eth port0 led and link poll functions for all boardsWeijie Gao
This patch adds default p0led status and phy0 link polling for all boards. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: update reset controller node for mt7628Weijie Gao
This patch updates reset controller node for mt7628 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add default pinctrl for uart nodesWeijie Gao
This patch adds default pinctrl for uart nodes Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add pinctrl node for mt7628Weijie Gao
This patch adds pinctrl node with default pin state for mt7628an.dtsi. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add clock node for mt7628Weijie Gao
This patch adds clkctrl node for mt7628 and adds clocks property for some node. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: enable high-speed UART support for mt7628Weijie Gao
All three UARTs of mt7628 are actually MediaTek's high-speed UARTs which support baudrate up to 921600. The high-speed UART is compatible with ns16550 when baudrate <= 115200. Add compatible string to dtsi file so u-boot can use it when serial_mtk driver is built in. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: move uart property clock-frequency into mt7628an.dtsiWeijie Gao
The UART of MT7628 has fixed 40MHz input clock so there is no need to put clock-frequency in every dts files. Just put it into the common dtsi file. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25mips: bmips: switch to board defines for dtbÁlvaro Fernández Rojas
Fixes commit 344db3f, which added missing bmips dtbs depending on their SoCs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: correct name charactersÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: enable vr-3032u nand supportÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: bcm63268: add support for brcmnandÁlvaro Fernández Rojas
BCM63268 uses 4.0 HW nand controller, which is currently supported by brcmnand driver. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: bcm6362: add support for brcmnandÁlvaro Fernández Rojas
BCM6362 uses old 2.2 HW nand controller, which isn't currently supported by brcmnand driver. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: bcm6328: add support for brcmnandÁlvaro Fernández Rojas
BCM6328 uses old 2.2 HW nand controller, which isn't currently supported by brcmnand driver. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: bcm6368: add support for brcmnandÁlvaro Fernández Rojas
BCM6368 uses old 2.1 HW nand controller, which isn't currently supported by brcmnand driver. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25MIPS: add compile time definition of L2 cache sizeRamon Fried
If configuration is set to skip low level init, automatic probe of L2 cache size is not performed and the size is set to 0. Flushing or invalidating the L2 cache will fail in this case. Add a static configuration (SYS_DCACHE_LINE_SIZE) with default set to 0. Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
2019-10-25sunxi: set PIO voltage to hardware-detected value on startup on H6Icenowy Zheng
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When it mismatches the real voltage supplied to the VCC to the PIO supply, the PIO will work improperly. The PIO controller also has a register that contains the status of each VCC rail of the PIO supplies, and it has the same definition with the configuration register. so we can just copy the content of this register to the configuration register at startup, to ensure the configuration is correct at startup stage. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> [jagan: s/__maybe__unused/__maybe_unused] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25arm: dts: sync dts for Allwinner H6Clément Péron
Sync Kernel DTS for Allwinner H6 boards. Drop /omit-if-no-ref/ keyword as it's not supported by U-boot. commit <d45331b00ddb> Linux 5.3-rc4 Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25sunxi: Fix pll1 clock calculationStefan Mavrodiev
clock_sun6i.c is used for sun6i, sun8i and sun50i SoC families. PLL1 clock sets the default system clock, defined as: sun6i: 1008000000 sun8i: 1008000000 sun50i: 816000000 With the current calculation, m = 2 and k = 3. Solving for n, this results 28. Solving back: (24MHz * 28 * 3) / 2 = 1008MHz However if the requested clock is 816, n is 22.66 rounded to 22, which results: (24MHz * 28 * 3) / 2 = 792MHz Changing k to 4 satisfies both system clocks: (24E6 * 21 * 4) / 2 = 1008MHz (24E6 * 17 * 4) / 2 = 816MHz Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25arm64: dts: sun50i: Add support for A64 OLinuXino (with eMMC)Sunil Mohan Adapa
A64 OLinuXino board from Olimex has three variants with onboard eMMC: A64-OLinuXino-1Ge16GW, A64-OLinuXino-1Ge4GW and A64-OLinuXino-2Ge8G-IND. In addition, there are two variants without eMMC. One without eMMC and one with SPI flash. This suggests the need for separate device tree for the three eMMC variants. The Linux kernel upstream has chosen to create and use a separate device tree for the eMMC variants instead of adding eMMC support existing device tree. These changes to Linux kernel are queued for Linux 5.4. commit <02bb66b347ff8115f53948f86b884e008ba385b9> ("arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)") This patch has been tested on A64-OLinuXino-1Ge16GW and is based on Linux device-tree and a64-olinuxino_defconfig. Signed-off-by: Sunil Mohan Adapa <sunil@medhas.org> [jagan: updated linux-next commit details] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25sunxi: H6: DRAM: Add support for half DQJernej Skrabec
Half DQ configuration seems to be very rare for H6 based boards/STBs, but exists nevertheless. Currently the only known product which needs this support is Tanix TX6 mini. This commit adds support for half DQ configuration. Code was tested for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix TX6 4 GiB/DDR3) and none were found. Thanks to Icenowy Zheng for help with this code. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: thomas graichen <thomas.graichen@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Maxime Ripard <mripard@kernel.org>
2019-10-25configs: sopine-baseboard: Enable SPI-FLASHJagan Teki
SoPine has winbond SPI-FLASH, so enable the same in defconfig and add aliases for spi0 in -u-boot.dtsi Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit (git 2.34.1) at 2024-12-27 02:29:11 +0000