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path: root/board/freescale/p1_p2_rdb/ddr.c
AgeCommit message (Expand)Author
2010-06-2985xx/p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHzPoonam Aggrwal
2009-10-2785xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data ratePoonam Aggrwal
2009-10-2785xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.Poonam Aggrwal
2009-09-24ppc/85xx: 32bit DDR changes for P1020/P1011Poonam Aggrwal
2009-09-08ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala
2009-08-2885xx: Add support for P2020RDB boardPoonam Aggrwal