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2013-02-20SMDK5250: Add PMIC voltage settingsRajeshwari Shinde
This patch adds required pmic voltage settings for SMDK5250. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-02-14x86: Remove eNET boardsSimon Glass
These are no longer used and should be removed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-12am335x_evm: Fix CPSW ethernet on GP EVM and EVM-SKTom Rini
In commit cfd4ff6 we implemented part of advisory 1.0.10 (internal delay for RGMII mode not supported). This in turn however requires that we set the tx clock delay feature in the PHY itself. Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2013-02-11Tegra114: Add/enable Dalmore build (T114 reference board)Tom Warren
This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11Tegra114: Add generic Tegra114 build supportTom Warren
This patch adds basic Tegra114 (T114) build support - no specific board is targeted. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11Tegra114: Dalmore: Add DT filesTom Warren
These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11tegra: add SPI SLINK driverAllen Martin
Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11tegra30: fdt: add SPI SLINK nodesAllen Martin
Add tegra30 SPI SLINK nodes to fdt. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11tegra20: fdt: add SPI SFLASH nodeAllen Martin
Add node for tegra20 SPI SFLASH controller to fdt. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11tegra: fdt: add back missing host1x nodeAllen Martin
Add back host1x node to seaboard dts file. This got dropped during the tegra fdt sort. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-08Clean up libfdt.h includesGerald Van Baren
The libfdt.h file is the definition file for libfdt. It is unnecessary to include other fdt header files (the necessary ones are pulled in by libfdt.h). Signed-off-by: Gerald Van Baren <gvb@unssw.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de>
2013-02-07am33xx: Drop gpio0_7_pin_mux from phytec pcm051Tom Rini
This mux is not currently used and appears to be a carry-over from the am335x evm code. Acked-by: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com>
2013-02-07OMAP3: igep00x0: fix a build warning on IGEP boardsJavier Martinez Canillas
commit b689cd5 OMAP3: use a single board file for IGEP devices introduced the following build warning: igep00x0.h:168:24: warning: backslash-newline at end of file [enabled by default] This patch fixes the issue. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
2013-02-07Add DDR3 support for AM335x-EVM (Version 1.5A)Jeff Lance
AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the DDR3 chip. [Hebbar Gururaja <gururaja.hebbar@ti.com>] - Resolve merge conflict while rebasing. File structure is changed in the mainline. So re-arrange the code accordingly. - Update commit message to reflect the DDR3 part number Signed-off-by: Jeff Lance <j-lance1@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
2013-02-07am335x: display msg when reading MAC from efuseLars Poeschel
When ethaddr is not set in environment the MAC address is read from efuse. The message was only printed in debug case, but this message could be of interest for the ordinary user, so printf it. Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
2013-02-07pcm051: Add support for Phytec phyCORE-AM335xLars Poeschel
The board is named pcm051 and has this hardware: SOC: TI AM3359 DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB ETH 1: LAN8710AI SPI-Flash: W25Q64BVSSIG RTC: RV-4162-C7 I2C-EEPROM: CAT32WC32 NAND: MT29F4G08_VFPGA63 PMIC: TPS65910A3 LCD Supported: UART 1 MMC/SD ETH 1 USB I2C SPI Not yet supported: NAND RTC LCD Signed-off-by: Lars Poeschel <poeschel@lemonage.de> [trini: Add #define CONFIG_PHY_ADDR 0 to config] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-07OMAP3: igep00x0: add boot status GPIO LEDJavier Martinez Canillas
This patch adds an GPIO LED boot status for IGEP boards. The GPIO LED used is the red LED0 while the Linux kernel uses the green LED0 as the boot status. By using different GPIO LEDs, the user can know in which step of the boot process the board currently is. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2013-02-07OMAP3: use a single board file for IGEP devicesJavier Martinez Canillas
Even when the IGEPv2 board and the IGEP Computer-on-Module are different from a form factor point of view, they are very similar in the fact that share many components and how they are wired. So, it is possible (and better) to have a single board file for both devices and just use the CONFIG_MACH_TYPE to make a differentiation between each board when needed. This change avoids code duplication by removing 298 lines of code and makes future maintenance easier. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2013-02-04Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini
2013-02-04board sc3: fix warning about nested commentJeroen Hofstee
cc: Heiko Schocher <hs@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2013-02-04ppc: Move kbd_status to arch_global_dataSimon Glass
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: Move wdt_last to arch_global_dataSimon Glass
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: Move fpga_state to arch_global_dataSimon Glass
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: Move mirror_hack to arch_global_dataSimon Glass
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: Move mpc5xxx clocks to arch_global_dataSimon Glass
Move ipb_clk and pci_clk into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04ppc: Move lbc_clk and cpu to arch_global_dataSimon Glass
Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Update for bsc9132qds.c, b4860qds.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-04microblaze: Remove FSL support from generic boardMichal Simek
This code was targetting one specific Microblaze platform configuration which is obsolete and fsl bus isn't used in this way. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-04board: xilinx: Remove common folderMichal Simek
All these files was used for ancient xilinx drivers which are finally gone. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Rommel Custodio <sessyargc@gmail.com>
2013-02-04board: xilinx: Remove unused ancient i2c driverMichal Simek
There is new driver in the driver folder. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Rommel Custodio <sessyargc@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
2013-02-03ARM: highbank: use wfi macro instead of inline asmRob Herring
Older compilers don't recognize v7 wfi instruction, so use wfi macro to fix builds on old compilers. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-02-02arm: rmobile: kzm9g: Adjust ETM trace clockTetsuyuki Kobayashi
Set ETM TRCLK down to 78MHz to get clear wave form. This patch makes difference only when you use ETM trace connecting JTAG debugger. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-02-02arm: rmobile: kzm9g: Adjust SDRAM settingTetsuyuki Kobayashi
After stress test, I found some of kzm9g board occures memory failure. This patch adust SDRAM setting. - Enlarge drivability on both SDRAM controller and SDRAM itself - Raise core voltage Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-02-02Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-01-30Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2013-01-31MIPS: qi_lb60: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. The qi_lb60 target produces a slightly different image after the change than before. The value of 'num_got_entries' symbol is different: @@ -49,7 +49,7 @@ 801000b4: 80122d00 lb s2,11520(zero) 801000b8: 80123500 lb s2,13568(zero) 801000bc: 80123ef8 lb s2,16120(zero) -801000c0: 00000139 0x139 +801000c0: 00000136 tne zero,zero,0x4 801000c4 <in_ram>: 801000c4: 8d0bfffc lw t3,-4(t0) This is caused by the different placement of the '__got_start' and '__got_end' symbols between the board specific scrip and the unified script. board specific script: __got_start = .; .got : { *(.got) } __got_end = .; unified script: .got : { __got_start = .; *(.got) __got_end = .; } Despite this difference, the resulting images are functionally identical. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-31MIPS: dbau1x00: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All dbau1x00 targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-31MIPS: incaip: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All incaip targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de>
2013-01-31MIPS: vct: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All vct targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-31MIPS: pb1x00: remove custom u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All pb1x00 targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-31MIPS: qemu-mips: use the unified u-boot.lds scriptGabor Juhos
Remove the board specific linker script. It is not needed anymore, the unified MIPS linker script can be used instead. All qemu_mips targets are producing identical binary images after the change than before. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-30MIPS: remove OUTPUT_FORMAT from linker scriptsGabor Juhos
The OUTPUT_FORMAT command in linker scripts was always misused due to some endianess and toolchain problems. Use GCC flags to ensure proper output format, and get rid of the OUTPUT_FORMAT commands in the board specific u-boot.lds files. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-01-30board/common: Add support for QIXIS read/write using i2cPrabhakar Kushwaha
QIXIS FPGA is accessable via both i2c and flash controller. Only flash controller access is supported. Add support of i2c based access. It is quite useful in the scenario where either flash controller path is broken or not present. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/85xx: Add BSC9132QDS supportPrabhakar Kushwaha
BSC9132QDS is a Freescale reference design board for BSC9132 SoC. BSC9132 SOC is an integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. BSC9132QDS Overview -------------------- 2Gbyte DDR3 (on board DDR), Dual Ranki 32Mbyte 16bit NOR flash 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory SD slot USB-ULPI eTSEC1: Connected to SGMII PHY eTSEC2: Connected to SGMII PHY PCIe CPRI SerDes I2C RTC DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/p2041: add RCW file for P2041RDBValentin Longchamp
All the dev boards of Freescale's QorIQ family have a RCW that is supported by the u-boot.pbl build target. This patch adds one for the P2041 dev board. This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/t4240qds: Print FPGA detail versionPrabhakar Kushwaha
Qixis FPGA has tag data contains image name and build date. It is helpful to identify the FPGA image precisely. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/t4240qds: Add support to dump switch settings on t4240qds boardShaveta Leekha
This function is called by "qixis_reset switch" command and switch settings are calculated from qixis FPGA registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/b4860qds: Add support to dump switch settings on b4860qds boardShaveta Leekha
This function is called by "qixis_reset switch" command and switch settings are calculated from FPGA/qixis registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/qixis: enable qixis dump command and add switch dumping commandShaveta Leekha
Remove #ifdef so that "qixis dump" command is always available Add "qixis_reset switch" command to dump switch settings Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from registers to figure out switch settings. Not all bits are available. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30powerpc/b4860qds: Added Support for B4860QDSYork Sun
B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor. B4860QDS Overview ------------------ - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB of memory in two ranks of 2 GB. - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank. - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch VSC3316 - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308 - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode. - B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable. - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for AMC mode. - The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The RCW source is set by appropriate DIP-switches: - 16-bit NOR Flash / PROMJet - QIXIS 8-bit NOR Flash Emulator - 8-bit NAND Flash - 24-bit SPI Flash - Long address I2C EEPROM - Available debug interfaces are: - On-board eCWTAP controller with ETH and USB I/F - JTAG/COP 16-pin header for any external TAP controller - External JTAG source over AMC to support B2B configuration - 70-pin Aurora debug connector - QIXIS (FPGA) logic: - 2 KB internal memory space including - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1, 2 and RTCCLK. - Two 8T49N222A SerDes ref clock devices support two SerDes port clocks - total four refclk, including CPRI clock scheme Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit (git 2.34.1) at 2025-01-11 10:53:20 +0000