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2016-06-12arm: dra7xx: Assign omap_vcores based on board typeKeerthy
Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-12Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
2016-06-10armv8: ls2080aqds: Enable QSPI boot supportYuan Yao
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND bootYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enableYuan Yao
When QSPI is enabled, NOR flash and QIXIS can't be accessed through IFC due to pin mux. Enable I2C QIXIS access and I2C early init to read the sysclk and ddrclk. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: Select QSPI CLK div via SCFGYuan Yao
QSPI module output SCLK divisor value is configured through SCFG. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10board: ls2080a: Add "mcinitcmd" env for MC & DPL deploymentPratiyush Mohan Srivastava
Environment variable mcinitcmd is defined to initiate MC and DPL deployment from the location where it is stored (NOR, NAND, SD, SATA, USB) during booting. If this variable is not defined then macro MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied during U-boot booting. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-09siemens,am33x: add draco etamin boardHeiko Schocher
In the draco CPU board family, etamin is a new variant with bigger flash and more RAM. Due to new flash that uses larger pages (4K) some changes are necessary because it impacts the MTD partition layout and the ubi mount parameters. Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Move BOOTDELAY into defconfig, just always be 3 now] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-06-09am335x, dxr2: get ECC sType from I2C eepromHeiko Schocher
read the ECC Type field from the i2c eeprom, instead configuring it static in the U-Boot binary. see RM: Table 26-17. NAND Geometry Information on I2C EEPROM Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09am335x, shc: add support for the am335x based bosch shc boardHeiko Schocher
U-Boot SPL 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:40:06) SHC C3-Sample MPU reference clock runs at 6 MHz Setting MPU clock to 594 MHz Enabling Spread Spectrum of 18 permille for MPU Trying to boot from MMC reading u-boot.img reading u-boot.img U-Boot 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:05:35 +0100) Watchdog enabled I2C: ready DRAM: 512 MiB reloc off 1f783000 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Net: cpsw U-Boot# Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-07board: ge: bx50v3: don't configure the backlight when there's no displayAndrew Shadura
Don't try to configure the backlight when CONFIG_VIDEO_IPUV3 isn't set. Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>
2016-06-06Merge http://git.denx.de/u-boot-samsungTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig
2016-06-06ARM: DRA7xx: Enable FIT for hs platformsLokesh Vutla
Use a single defconfig for all DRA7xx hs platforms by enabling FIT and delete the platform specific defconfigs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-06-06strider: Support con-dp flavorDirk Eibach
There is a new strider console flavor with DisplayPort video. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-06gdsys: osd: Allow osdsize on valid screens onlyDirk Eibach
Limit "osdsize"-command to access valid screens only. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-06ioep-fpga: Support intempo compressionDirk Eibach
There is a new "intempo" compression type that can be reported on startup. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-06Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini
2016-06-06ARM64: zynqmp: Add support for standard distro boot commandsMichal Simek
Nand and QSPI are not defined now but this will be extended. Based on selected bootmode boot_targets are rewritten. Patch also contains detection if variables are saved. If yes don't rewrite boot_targets variable. Also move variable setup to the end of file because SCSI needs to be defined before others macros are using it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Alexander Graf <agraf@suse.de>
2016-06-06microblaze: Move MSR instruction selection to KconfigMichal Simek
Select MSR instructions via Kconfig instead of xparameters.h. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-06-06microblaze: Add option to pass cpu version numberMichal Simek
Toolchain can use some flags by default based on cpu version. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-06-06microblaze: Select compilation flags via KconfigMichal Simek
Remove autogenerated config.mk and select CPU options via Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-06-04Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini
2016-06-04Merge git://git.denx.de/u-boot-nand-flashTom Rini
2016-06-04Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
2016-06-03freescale: Tweak various Makefiles to remove redundancy, fix aestheticsRobert P. J. Day
No intended functional change, just remove redundancies in some Makefiles, and make whitespace aesthetics uniform. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl bootShengzhou Liu
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot to make sure 'M' bit is set for DDR TLB to maintain cache coherence. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03powerpc/board: SPL: Enable malloc flag in global data.Sumit Garg
For malloc to work in SPL framework enable GD_FLG_FULL_MALLOC_INIT flag in global data after allocating memory using mem_malloc_init. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_dataScott Wood
These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03nand: Embed mtd_info in struct nand_chipScott Wood
nand_info[] is now an array of pointers, with the actual mtd_info instance embedded in struct nand_chip. This is in preparation for syncing the NAND code with Linux 4.6, which makes the same change to struct nand_chip. It's in a separate commit due to the large amount of changes required to accommodate the change to nand_info[]. Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03armv8: ls1012a: Add support of ls1012afrdm boardPrabhakar Kushwaha
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development platform, with a complete debugging environment. The LS1012AFRDM board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: ls1012a: Add support of ls1012ardb boardPrabhakar Kushwaha
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: ls1012a: Add support of ls1012aqds boardPrabhakar Kushwaha
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03board: freescale: common: Add flag for LBMAP brdcfg reg offsetAbhimanyu Saini
Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP configuration register instead of hardcoding it in set_lbmap() function. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03board: freescale: common: Conditionally compile IFC QXIS funcAbhimanyu Saini
Check if qixis supports memory-mapped read/write before compiling IFC based qixis read/write functions. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: fsl-layerscape: Organize SoC overview at common locationPrabhakar Kushwaha
SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc Also move README.lsch2 and README.lsch3 in same folder. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: ls1043aqds: fix usb PWRFAULT settingShaohui Xie
SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should be used for USB 3 & 2. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not definedYork Sun
U-Boot should continue to work without management complex (MC). Fix compiling errors and warnings. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-03board: ls102xa: Fix ICID setupVincent Siles
LS102A ref manual dictates that ICID have to be written to the MSB of the ICID register, not to the LSB. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
2016-06-03board/freescale: Update ddr clk_adjustShengzhou Liu
This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2016-06-02Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2016-06-02ARM: k2g: Configure reset mux to device resetLokesh Vutla
BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM. Timer5(dedicated to ARM) when used as WatchDog timer, the events it generates are routed to the above mux. Following are the 3 events that can controlled bt the reset mux: - Device Reset - An interrupt to the ARM_GIC - An interrupt to the ARM_GIC followed by a device reset. Right now to give a default watchdog behaviour "Device reset" is being selected. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
2016-06-02arm: am57xx: Fix alignment where necessaryKeerthy
This just fixes alignment for better readability. Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-02arm: am57xx: Fix omap_vcores assignment for am572x-idkKeerthy
Currently omap_vcores is wrongly assigned a default value of beagle_x15_volts. Hence populating a new structure for am572x-idk and assigning it to omap_vcores in the vcores_init function. Fixes: c020d355c45ed40fe12a ("board: ti: am57xx: Add support for am572x idk in SPL") Reported-by: Suman Anna <s-anna@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-02ARM: DRA7: Consolidate voltage macros across different SoCsAnna, Suman
The voltage values for each voltage domain at an OPP is identical across all the SoCs in the DRA7 family. The current code defines one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x macros. Consolidate both these sets into a single set. This is done so as to minimize the number of macros used when voltage values will be added for other OPPs as well. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-06-02ARM: DRA7: Define common macros for efuse register offsetsAnna, Suman
Define a set of common macros for the efuse register offsets (different for each OPP) that are used to get the AVS Class 0 voltage values and ABB configuration values. Assign these common macros to the register offsets for OPP_NOM by default for all voltage domains. These common macros can then be redefined properly to point to the OPP specific efuse register offset based on the desired OPP to program a specific voltage domain. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-06-02ARM: AM57xx: AM43xx: Fix USB hostRoger Quadros
CONFIG_USB_XHCI_OMAP can be set for host mode without setting CONFIG_USB_DWC3 which is meant for gadget mode only. board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP resulting in a data abort on usb start. Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move gadget specific handling to within CONFIG_USB_DWC3. Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks") Signed-off-by: Roger Quadros <rogerq@ti.com>
2016-06-01arm: socfpga: Add samtec VIN|ING boardMarek Vasut
Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
2016-05-31ARM: tegra: add p2771-0000 board supportStephen Warren
P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO expansion headers. Currently, due to U-Boot's level of support for Tegra186, the only features supported by U-Boot are the console UART and the on-board eMMC. Additional features will be added over time. U-Boot has so far been tested by replacing the kernel image on the device with a U-Boot binary. It is anticipated that U-Boot will eventually replace the CCPLEX bootloader binary, as on previous chips. This hasn't yet been tested. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-05-31ARM: tegra: use DT bindings for GPIO namingStephen Warren
There are currently many places that define the list of all Tegra GPIOs; the DT binding header and custom Tegra-specific header file gpio.h. Fix the redundancy by replacing everything with the DT binding header file. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit (git 2.34.1) at 2024-12-24 01:55:16 +0000