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path: root/cpu/mpc85xx
AgeCommit message (Expand)Author
2009-11-13ppc/85xx: Fix how we determine the number of CAM entriesKumar Gala
2009-10-31ppc/85xx: Fix misc L2 cache enabling bugDave Liu
2009-10-28Coding Style cleanup; update CHANGELOG, prepare -rc1Wolfgang Denk
2009-10-27mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov
2009-10-2785xx: MP Boot Page Translation updatePeter Tyser
2009-10-26ppc/85xx: Fix crashes due to generation of SPE instructionLeon Woestenberg
2009-10-26ppc/85xx: Make L2 support more robustDave Liu
2009-10-08relocation: Do not relocate NULL pointers.Joakim Tjernlund
2009-10-0885xx: Ensure BSS segment isn't linked at address 0Peter Tyser
2009-10-03ppc: Enable full relocation to RAMPeter Tyser
2009-09-24ppc/p4080: Determine various chip frequencies on CoreNet platformsKumar Gala
2009-09-24ppc/p4080: Handle timebase enabling and frequency reportingKumar Gala
2009-09-24ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala
2009-09-24ppc/p4080: CoreNet platfrom style secondary core releaseKumar Gala
2009-09-24ppc/p4080: CoreNet platfrom style CCSRBAR settingKumar Gala
2009-09-24ppc/85xx: Fix enabling of L2 cacheKumar Gala
2009-09-2485xx-fdt: Fixed l2-ctlr's compatible prop for QorIQVivek Mahajan
2009-09-24ppc/85xx: add cpu init config file for boot from NANDMingkai Hu
2009-09-24ppc/85xx: add ld script file for boot from NANDMingkai Hu
2009-09-15ppc/85xx: Disable all async interrupt sources when we bootKumar Gala
2009-09-15ppc/85xx: Split out cpu_init_early into its own file for NAND_SPLKumar Gala
2009-09-15ppc/85xx: Change cpu_init_early_f so we can use with NAND SPLKumar Gala
2009-09-15ppc/85xx: add boot from NAND/eSDHC/eSPI supportMingkai Hu
2009-09-15ppc/85xx: Move code around to prep for NAND_SPLKumar Gala
2009-09-15ppc/85xx: Repack tlb_table to save spaceKumar Gala
2009-09-15ppc/85xx: Introduce low level write_tlb functionKumar Gala
2009-09-15ppc/85xx: Remove some bogus code from external interrupt handler.Scott Wood
2009-09-15ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.Scott Wood
2009-09-15ppc/85xx: Don't enable interrupts before we're readyScott Wood
2009-09-09ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link addressKumar Gala
2009-09-08ppc/85xx: Clean up do_resetKumar Gala
2009-09-08ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().Poonam Aggrwal
2009-09-08ppc/85xx/86xx: Device tree fixup for number of coresPoonam Aggrwal
2009-09-08ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal
2009-09-08ppc/85xx: Cleanup makefile and related optional filesKumar Gala
2009-09-08ppc/85xx: Fix bug in setup_mp codeKumar Gala
2009-09-08ppc/85xx: Add a simple function to search the TLBKumar Gala
2009-09-0885xx: Add support for setting IVORs to fixed offset defaultsKumar Gala
2009-09-08ppc/85xx: Fix up eSDHC controller clock frequency in the device treeDipen Dudhat
2009-09-08ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala
2009-09-08ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clkDipen Dudhat
2009-08-2885xx: Improve MPIC initializationTimur Tabi
2009-08-2885xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal
2009-08-2885xx: Add L2SRAM Register's macro definitionMingkai Hu
2009-08-2885xx: Move to a common linker scriptKumar Gala
2009-08-2885xx: Added P1020 Processor Support.Poonam Aggrwal
2009-08-288xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal
2009-08-288xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal
2009-08-2885xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala
2009-08-22Prepare 2009.08-rc3Wolfgang Denk
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