| Age | Commit message (Collapse) | Author |
|---|
|
The standard Altera UART & JTAG UART as well as the OpenCores
YANU driver are now in individual files in drivers/serial
rather than a single file uner cpu/nios2.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
|
|
|
|
|
|
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way. If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).
Currently we are limited to power of two sized DDR since we only use a
single bat. If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
|
Use the same code between primary and secondary cores to init the
L1 cache. We were not enabling cache parity on the secondary cores.
Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks. Than enables the cache and
makes sure its enabled before continuing.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
|
This patch fixes a problem introduced with patch eb5eb2b0
[ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C
base address to the "i2c" pointer inside of the controller loop.
Otherwise controller 0 is initialized multiple times instead of
initializing each I2C controller sequentially.
Tested on Katmai.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
|
|
|
|
The CF will call cache functions in lib_m68/cache.c and the
cache settings are defined in platform configuration file.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
|
|
Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add
CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update
DRAM control and SRAM control register setting. Update cache
setting where size does not write to proper region.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
|
|
Add CPU compile flag -mcpu=53015 in cpu/config.mk
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
|
|
Newer ColdFire processors family boot from address 0 instead of
0xFFnn_nnnn. When the boot flash base chip select is set at new
location instead of 0, an un-predictable error will occur if
there is an vector being trigger and refer it to an invalid
address or the vector table handler is not existed at address
0.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
|
|
Provide parameter passing to uart_port_config(). Update port
configuration - un-mask it before enable the bits.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
|
|
Use correct definition for _MASK and _UNMASK. It was combined in
the previous used and causes confusion.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
|
|
Mercury-EP2500.patch
- added Mercury's EP2500 board uses the mcf5282 processor
CREDITS.patch
Signed-off-by: David Wu <davidwu@arcturusnetworks.com>
Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com>
|
|
440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1.
This results in the PLLOUTB being greater than the CPU clock frequency
resulting unstable 440EPx operation resulting in various software hang
conditions.
This patch reprograms the FWDVA satisfying the requirement of setting FWDVB
to a value greater than 1 while using one of the four deafult bootstrap options.
Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
Acked-by : Victor Gallardo <vgallardo@appliedmicro.com>
Signed-off-by: Stefan Roese <sr@denx.de>
|
|
|
|
ep93xx timer: Make get_ticks() return a value in CONFIG_SYS_HZ resolution,
as announced by get_tbclk()
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
|
|
ep93xx timer: Use 64-bit values in usecs_to_ticks() in order to avoid
overflows in intermediate values
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
|
|
|
|
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
|
|
We do not support a processor that never reached a real customer.
Signed-off-by: Detlev Zundel <dzu@denx.de>
|
|
Fix warnings while compiling with CONFIG_VIDEO enabled:
diu.c: In function 'video_hw_init':
diu.c:158: warning: 'return' with no value, in function returning non-void
diu.c:162: warning: format '%ld' expects type 'long int', but argument 6 has type 'int'
diu.c:162: warning: format '%ld' expects type 'long int', but argument 7 has type 'int'
Signed-off-by: Anatolij Gustschin <agust@denx.de>
|
|
I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;'
Signed-off-by: Thomas Weber <swirl@gmx.li>
Add some more: neither Makefile nor config.mk need execute permissions.
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
|
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
|
|
Coding style cleanup, update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
|
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
|
* updates the conditional main_clock calculation (if AT91_MAIN_CLOCK defined) to c structure SoC access
* add need register flags
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
|
|
The patch removes warnings at compile time and provides
some cleanup code:
- Removed comment on NAND (not yet supported) from lowlevel_init.S
- Removed NFMS bit definition from imx-regs.h
The bit is only related to MX.25/35 and can lead to confusion
- Moved is_soc_rev() to soc specific code (removed from mx51evk.c)
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
|
general cleanup
move clock init to cpu_eth_init in cpu/arm926ejs/mx27/generic.c
make MX27 specific phy init conditional on CONFIG_MX27
replace call to imx_get_ahbclk with one to imx_get_fecclk
and define imx_get_fecclk in include/asm-arm/arch-mx27/clock.h
Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>
|
|
ARM926EJS core with MX31 peripherals.
Signed-off-by: John Rigby <jcrigby@gmail.com>
Earlier Version Signed-off-by: Wolfgang Denk <wd@denx.de>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>
|
|
The esdhc controller in the mx51 processor is quite
the same as the one in some powerpc processors
(MPC83xx, MPC85xx). This patches adapts the driver
to support the arm mx51.
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
|
The patch add initial support for the Freescale i.MX51 processor
(family arm cortex_a8).
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fred Fan <fanyefeng@gmail.com>
|
|
Use AT91_GPBR 3 as a bootcount register.
The bootmagic and the bootcount shares AT91_GPBR 3.
Signed-off-by: Anders Darander <ad@datarespons.se>
|
|
ep93xx: Refactoring of the timer code, including the following changes
* use a free running timer instead of a periodical one
* use unsigned long long for total number of ticks
* hold the timer state in a structure instead of separate variables
* increment the timer counter instead of decrementing it
* remove unused function udelay_masked()
* remove unused function set_timer()
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
|
|
ep93xx: Use unsigned long long for calculation of sys ticks in clk_to_systicks()
for proper handling of large intermediate values
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
|
|
725233: PLD instructions executed with PLD data forwarding
enabled can result in a processor deadlock
This deadlock can happen when NEON load instructions are used together
with cache preload instructions (PLD). The problematic conditions
can be triggered in-the-wild by NEON optimized functions from pixman
library (http://cgit.freedesktop.org/pixman), which perform dynamic
adjustment of prefetch distance.
The workaround disables PLD data forwarding by setting PLD_FWD bit
in L2 Cache Auxiliary Control Register as recommended in ARM Cortex-A8
errata list.
The deadlock can only happen on r1pX revisions of Cortex-A8 (used in
OMAP34xx/OMAP35xx). Performance impact of the workaround is practically
non-existant.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
|
|
Configuration defines should be preceeded with CONFIG_SYS_. Renamed
some at91 specific defines to conform to this naming convention:
AT91_CPU_NAME to CONFIG_SYS_AT91_CPU_NAME
AT91_MAIN_CLOCK to CONFIG_SYS_AT91_MAIN_CLOCK
Signed-off-by: Achim Ehrlich <aehrlich@taskit.de>
|
|
|
|
CONFIG_MONITOR_IS_IN_RAM is broken for MCF532x. This patch fixes this
by conditionally
- removing the vector table at the beginning of code
- not overwriting the vector base register
- removing the code to re-set the PLL, which effectively disables
SDRAM access
Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
|
|
This patch adds a board_reset function to allow boards to specify
their own custom reset sequence (e.g. resetting by timing out watchdog).
Tested only on MCF5271, can be expanded if needed.
Based on Mike Frysinger's suggestion on:
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/70304
Signed-off-by: Richard Retanubun <RichardRetanubun at RuggedCom.com>
|
|
in cpu/mcf532x/start.S, the function icache_enable enables the cache for
a fixed 32MB region starting at the SDRAM start address; this patch
changes the function to cover the region defined by CONFIG_SYS_SDRAM_SIZE
Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
|
|
The do_reset routine in the cpu/mpc83xx/cpu.c file does not reset
the mpc83xx cpu when issued via netconsole.
Moving the console output "resetting the board." to the beginning of
the routine before disabling interrupts solved the problem.
Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com>
Acked-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
|
* prepare joining at91 and at91rm9200
* add modified copy of soc files to cpu/arm920t/at91 to make
possible to compile at91rm9200 boards in at91 tree instead
of at91rm9200
* add header files with c structure defs for AT91 MC, ST and TC
* the new cpu files are using at91 c structure soc access
* please read README.soc-at91 for details
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
|
|
* add's a warning to all files, which need update to new SoC access
* convert common files in cpu/../at91 and a lot of drivers to use
c stucture SoC access
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
|
|
* convert all files cpu/../at91 to use at91_gpio driver syntax
* change AT91_PINP([A-F])(\d+) to AT91_PIO_PORT\1, \2
this makes all 160 AT91_PINPxxx defines obsolete
* AT91_PINPxxx defines and gpio.h can be remove, if all boards converted to new SoC access
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
|
|
In function get_osc_clk_speed(), do not change/ update
the divider for SYS_CLK as it can has cascading effect
on the other derived clocks.
Sudden change in divider value can lead to inconsistent
behavior in the system - often leading to crashes.
The problem was found when working with OMAP3EVM using
DM3730 processor card.
The patch has been tested with OMAP3530 on OMAP3EVM as
well
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Hiremath Vaibhav <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
|
|
Add support for the Cirrus EP93xx platform
Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Acked-by: Tom <Tom.Rix@windriver.com>
|
|
Commit cbb0cab1d929839d broke some platforms which used kgdb code but
didn't actually include kgdb.h. So include kgdb.h in all the relevant
traps code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
|
|
|
