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path: root/drivers/clk/altera
AgeCommit message (Expand)Author
2020-04-05clk: socfpga: Read the clock parent's register base in probe functionChee Hong Ang
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass
2020-02-05dm: core: Require users of devres to include the headerSimon Glass
2020-01-07clk: agilex: Add clock driver for AgilexLey Foon Tan
2019-04-11clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay
2018-11-14clk: Remove DM_FLAG_PRE_RELOC flag in various driversBin Meng
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay
2018-08-13clk: socfpga: Add initial Arria10 clock driverMarek Vasut