Age | Commit message (Expand) | Author |
---|---|---|
2020-04-05 | clk: socfpga: Read the clock parent's register base in probe function | Chee Hong Ang |
2020-02-05 | dm: core: Create a new header file for 'compat' features | Simon Glass |
2020-02-05 | dm: core: Require users of devres to include the header | Simon Glass |
2020-01-07 | clk: agilex: Add clock driver for Agilex | Ley Foon Tan |
2019-04-11 | clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_reloc | Patrick Delaunay |
2018-11-14 | clk: Remove DM_FLAG_PRE_RELOC flag in various drivers | Bin Meng |
2018-10-28 | drivers: cosmetic: Convert SPDX license tags to Linux Kernel style | Patrick Delaunay |
2018-08-13 | clk: socfpga: Add initial Arria10 clock driver | Marek Vasut |