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Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
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Add new set_clr_upd mux type and related operation to
mtk common clock driver to support mt8512
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This adds high speed interface subsystem - hifsys (i.e. PCIe and USB)
for MT7623 SoC and enables its reset controller.
The control block is shared with ethsys and accordingly rename the
related defines.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
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The ethsys contains not only the clock gating controller, but also the
reset controller for the whole ethernet subsystem and its components.
This patch adds binding of the reset controller so that the ethernet node
can have references on it.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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