Age | Commit message (Expand) | Author |
---|---|---|
2018-01-24 | clk: renesas: Add Gen2 clock core | Marek Vasut |
2018-01-24 | clk: renesas: Add DIV6P1 clock type | Marek Vasut |
2018-01-24 | clk: renesas: Split out code shared between Gen2 and Gen3 | Marek Vasut |
2018-01-24 | clk: renesas: Split SMSTPCR and RMSTPCR tables | Marek Vasut |
2018-01-24 | clk: renesas: Pull Gen3 specific bits into separate header | Marek Vasut |
2018-01-24 | clk: renesas: Make PLL configurations per-SoC | Marek Vasut |
2018-01-24 | clk: renesas: Make clk_ids per-driver | Marek Vasut |
2018-01-24 | clk: renesas: Split RCar Gen3 driver | Marek Vasut |