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path: root/drivers/fpga
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2020-08-20xilinx: zynqmp: synchronize firmware call return payloadIbai Erkiaga
Removes duplicated definition of PAYLOAD_ARG_CNT and define it in the firmware driver. Additionally fixes payload buffer declarations without macro usage Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-03fs: fs-loader: Drop dm.h header fileSimon Glass
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-06-24arm64: xilinx: Print fpga error value in hexT Karthik Reddy
Fpga returns error value when fails, error status should be printed in hex format. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24fpga: zynqpl: Flush dcache only for non-bitstream dataT Karthik Reddy
In case of aes decryption destination address range must be flushed before transferring decrypted data to destination. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24fpga: zynqpl: Check if aes engine is enabledIbai Erkiaga
AES engine cannot be used if has not been enabled at boot time with an encrypted boot image. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24fpga: zynqpl: Check fpga config completionT Karthik Reddy
This patch checks fpga config completion when a bitstream is loaded into PL. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24fpga: zynqpl: Correct PL bitstream loading sequence for zynqaesSiva Durga Prasad Paladugu
Correct the PL bitstream loading sequence for zynqaes command by clearing the loaded PL bitstream before loading the new encrypted bitstream using the zynq aes command. This was done by setting the PROG_B same as in case of fpgaload commands. This patch fixes the issue of loading the encrypted PL bitstream onto the PL in which a bitstream has already been loaded successfully. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18Fix some checkpatch warnings in calls to udelay()Simon Glass
Fix up some incorrect code style in calls to functions in the linux/time.h header, mostly udelay(). Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop init.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop image.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07arm: socfpga: Convert system manager from struct to definesLey Foon Tan
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-12-02common: Move ARM cache operations out of common.hSimon Glass
These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02common: Move some cache and MMU functions out of common.hSimon Glass
These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-10-24arm64: zynqmp: Convert invoke_smc() to xilinx_pm_request()Michal Simek
Remove macros which use PM_SIP_SVC offset and convert invoke_smc() to xilinx_pm_request() which do calculation with PM_SIP_SVC already. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: versal: Rename versal_pm_request to xilinx_pm_requestMichal Simek
Use generic name instead of Versal specific because this should be also used on ZynqMP. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: xilinx: Move firmware functions from platform to driverMichal Simek
versal_pm_request() and invoke_smc() are almost the same. Only one difference is that versal_pm_request is adding PM_SIP_SVC offset to api_id. The patch is moving platform implementation to firmware driver code for synchronization. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2019-10-08arm64: zynqmp: use firmware driver to get versionIbai Erkiaga
Use the new function from firmware version to get the firmware version. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08firmware: zynqmp: create firmware headerIbai Erkiaga
New firmware header to place firmware specific macro and function declarations. The patch also moves the macros defining PM operations as well as some helper macros. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08fpga: zynqmp: Fix second local variable declarationMichal Simek
No reason to define new_buf again. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08arm64: versal: fpga: Add PL bit stream load supportSiva Durga Prasad Paladugu
This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: altera: cyclon2: Check function pointer before callingAlexander Dahl
As already done for the 'pre' function, a check is added to not follow a NULL pointer, if somebody has not assigned a 'post' function. Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30fpga: altera: cyclon2: Fix indentationAlexander Dahl
Some code parts stood too far left … Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30fpga: altera: cyclon2: Fix most checkpatch warningsAlexander Dahl
Nothing special, but done before further cleanup. * spacing * braces * __FUNCTION__ → __func__ Suggested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30fpga: virtex2: Add slave serial programming supportRobert Hancock
This adds support for slave serial programming, in addition to the previously supported slave SelectMAP mode. There are two ways that this can be used: -Using the clk and wdata callbacks in order to write image data one bit at a time using pure bit-banging. This works, but is rather painfully slow with typical image sizes. -By specifying the wbulkdata callback instead, the image loading process can be offloaded to SPI hardware. In this mode the clk and wdata callbacks do not need to be specified. This allows the image to be loaded much faster, taking only a few seconds with even relatively large images. Slave serial programming has been tested on the Kintex-7 series of FPGAs. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: virtex2: Add additional clock cycles after DONE assertionRobert Hancock
Some Xilinx FPGA configuration options can result in the startup sequence extending past the end of the FPGA bitstream. Continue applying CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure the startup sequence is complete, as recommended by Xilinx. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: virtex2: Split out image writing from pre/post operationsRobert Hancock
This is in preparation for adding slave serial programming support, which uses the same pre/post operations as slave SelectMAP, to avoid duplicating code. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: virtex2: added Kconfig optionRobert Hancock
Add an option to allow this driver to be selected with Kconfig. As noted in the description, this driver should also work with many newer Xilinx FPGA families as the programming methods are essentially the same. Also added a missing FPGA_XILINX dependency to the similar Spartan 3 driver. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30fpga: virtex2: cosmetic: Cleanup code styleRobert Hancock
Address Checkpatch warnings in virtex2 code prior to making other changes. No functional change intended. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-21fpga: arria10: Fix error in fpga pin configurationDalon Westergreen
Pin configuration of the FPGA devicetree block should be done after core configuration in the arria10 fpga driver. This fix corrects the check of status, and ensures that the fpga pin mux is configured on correct configuration of the core fpga image. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
2019-05-10spl: socfpga: Implement fpga bitstream loading with socfpga loadfsTien Fong Chee
Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loadingTien Fong Chee
Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10ARM: socfpga: Moving the watchdog reset to the for-loop status pollingTien Fong Chee
Current watchdog reset is misplaced after for-loop status polling, so this poses a risk that watchdog can't be reset timely if polling taking longer than watchdog timeout. This patch moving the watchdog reset into polling to ensure the watchdog can be reset timely. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10ARM: socfpga: Cleaning up and ensuring consistent format messages in driverTien Fong Chee
Ensure all the debug messages are always prefix with "FPGA: " and comment beginning with uppercase letter. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-16arm: zynq: Add an info message about post configSiva Durga Prasad Paladugu
Post configuration cant be run at u-boot as u-boot didn't has any info about the design.So,this patch adds an info message that post config was not run and needs to be run manually if needed. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-04-16fpga: Replace char * with const char * for filenameTien Fong Chee
Ensure the string for filename is always constant, otherwise it can be corrupted by the writing. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-18ARM: socfpga: stratix10: Return valid error code from FPGA driverAng, Chee Hong
This patch prevent the Stratix 10 FPGA driver incorrectly return the transaction ID as the mailbox error code. It should always return the actual mailbox error code from SDM firmware. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-01-24fpga: zynqmp: show an error message when FPGA programming failsLuca Ceresoli
When FPGA programming fails, it does so silently, unless debugging code is enabled. This makes it hard to detect problems in production environments. Print the error message unconditionally so the error doesn't go unnoticed. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-12-20arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device tableAng, Chee Hong
Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-12-20arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration DriverAng, Chee Hong
Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-10-31arm: socfpga: fpga: fix type of local variableSimon Goldschmidt
The 'status' variable in 'socfpga_load()' for both gen5 and arria10 is of type 'unsigned long' while it is always used as 'int' only. Change it to 'int'. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-09-26fpga: zynqmp: Modify PL bitstream loading sequenceSiva Durga Prasad Paladugu
This patch modifies PL bitstream loading sequence as per latest Xilfpga which supports all variants of bitstream images generated from vivado and from bootgen. With this new change in Xilfpga, uboot doesn't need to validate and swap bitstream as it will be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting PMUFW version before skipping the validation and swap sequence as there can be old PMUFW which doesn't supports this feature. In this case, driver uses old way of PL bitstream loading sequence. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-11fpga: Kconfig: Replace spaces with tabsMichal Simek
Trivial Kconfig cleanup. Use tabs instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19drivers: fpga: zynqpl: fix compilation with SPLLuis Araneda
Disable the use of function zynq_loadfs when compiling the driver for the SPL, as the following filesystem functions are not found by the linker: - fs_set_blk_dev - fs_read - fs_set_blk_dev - fs_read - fs_read Signed-off-by: Luis Araneda <luaraneda@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19xilinx: zynq: Add support to secure imagesSiva Durga Prasad Paladugu
This patch basically adds two new commands for loadig secure images. 1. zynq rsa adds support to load secure image which can be both authenticated or encrypted or both authenticated and encrypted image in xilinx bootimage(BOOT.bin) format. 2. zynq aes command adds support to decrypt and load encrypted image back to DDR as per destination address. The image has to be encrypted using xilinx bootgen tool and to get only the encrypted image from tool use -split option while invoking bootgen. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-01fpga: zynqmp: Add secure bitstream loading for ZynqMPSiva Durga Prasad Paladugu
This patch adds support for loading secure bitstreams on ZynqMP platforms. The secure bitstream images has to be generated using Xilinx bootgen tool. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2024-12-23 10:33:00 +0000