Age | Commit message (Expand) | Author |
2018-02-28 | arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL | Vipul Kumar |
2018-02-28 | fpga: Added Kconfig support for FPGA_SPARTAN3 | Vipul Kumar |
2018-01-24 | wait_bit: use wait_for_bit_le32 and remove wait_for_bit | Álvaro Fernández Rojas |
2017-12-14 | fpga: allow programming fpga from FIT image for all FPGA drivers | Goldschmidt Simon |
2017-11-26 | arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes | Tien Fong Chee |
2017-08-02 | fpga: xilinx: Avoid using local intermediate buffer | Siva Durga Prasad Paladugu |
2017-07-26 | arm: socfpga: Add FPGA driver support for Arria 10 | Tien Fong Chee |
2017-07-26 | kconfig: Convert FPGA_SOCFPGA configuration to Kconfig | Tien Fong Chee |
2017-07-26 | arm: socfpga: Restructure FPGA driver in the preparation to support A10 | Tien Fong Chee |
2017-06-20 | fpga: zynqmppl: Reuse invoke_smc routine | Siva Durga Prasad Paladugu |
2017-04-18 | FPGA: drivers/fpga/ivm_core.c: incorrect printf | xypron.glpk@gmx.de |
2017-01-10 | fpga: zynqmp: Remove empty functions | Michal Simek |
2016-12-16 | arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC | Patrick Bruenn |
2016-09-23 | treewide: replace #include <asm/errno.h> with <linux/errno.h> | Masahiro Yamada |
2016-09-22 | fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP | Siva Durga Prasad Paladugu |
2016-09-22 | fpga: Add Kconfig to fpga subsystem | Michal Simek |
2016-07-16 | Various, unrelated tree-wide typo fixes. | Robert P. J. Day |
2016-05-24 | fpga: Fix typo in function comment | Michal Simek |
2016-03-24 | fpga: altera: Add StratixV support | Stefan Roese |
2016-03-22 | Fix spelling of "transferred". | Vagrant Cascadian |
2016-02-04 | Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals" | Dinh Nguyen |
2016-01-27 | fpga: xilinx: Check for substring in device ID validation | Siva Durga Prasad Paladugu |
2016-01-16 | arm: socfpga: set the fpga global bit to disable HPS to FPGA signals | Dinh Nguyen |
2015-11-19 | Move console definitions into a new console.h file | Simon Glass |
2015-08-08 | arm: socfpga: Fix FPGA bitstream programming routine | Marek Vasut |
2015-01-21 | fpga: xilinx: Show fpga info if defined | Michal Simek |
2015-01-21 | fpga: xilinx: Check if fpga operations are defined | Michal Simek |
2015-01-21 | fpga: Export fpga_get_desc for SPL | Michal Simek |
2014-11-23 | fs: API changes enabling extra parameter to return size of type loff_t | Suriyan Ramasami |
2014-10-06 | arm: socfpga: fpga: Add SoCFPGA FPGA programming interface | Pavel Machek |
2014-10-06 | fpga: altera: Turn the switches into table lookup | Marek Vasut |
2014-10-06 | fpga: altera: Make altera_validate return normal values | Marek Vasut |
2014-10-06 | fpga: altera: Move altera_validate to the top | Marek Vasut |
2014-10-06 | fpga: altera: More indentation trimdown | Marek Vasut |
2014-10-06 | fpga: altera: Clean up altera_validate function | Marek Vasut |
2014-10-06 | fpga: altera: Clean up the printing and debug | Marek Vasut |
2014-06-11 | m68k: Fix warnings with gcc 4.6 | Simon Glass |
2014-05-20 | fpga: Added support to load bit stream from SD/MMC | Siva Durga Prasad Paladugu |
2014-05-20 | fpga: zynqpl: Clean partial bitstream handling | Michal Simek |
2014-05-20 | fpga: Define bitstream type based on command selection | Michal Simek |
2014-05-13 | fpga: zynq: Use helper function zynq_validate_bitstream | Siva Durga Prasad Paladugu |
2014-05-13 | fpga: zynq: Use helper functions for zynq dma | Siva Durga Prasad Paladugu |
2014-05-13 | fpga: zynq: Remove sparse warnings | Michal Simek |
2014-05-13 | fpga: xilinx: Simplify load/dump/info function handling | Michal Simek |
2014-05-13 | fpga: xilinx: Avoid CamelCase for in Xilinx_desc | Michal Simek |
2014-05-13 | fpga: virtex2: Avoid CamelCase | Michal Simek |
2014-05-13 | fpga: spartan3: Avoid CamelCase | Michal Simek |
2014-05-13 | fpga: spartan2: Avoid CamelCase | Michal Simek |
2014-03-04 | sizes.h - consolidate for all architectures | Alexey Brodkin |
2014-02-06 | fpga: zynq: Correct fpga load when buf is not aligned | Novasys Ingenierie |