summaryrefslogtreecommitdiff
path: root/drivers/mmc
AgeCommit message (Collapse)Author
2018-05-13mmc: Improve tinificationMarek Vasut
Drop all the extra content from the MMC core, so that tiny MMC support is really tiny, no fancy anything. That means the tiny MMC support does only 1-bit transfers at default speed settings. Moreover, this patch drops duplicate instance of struct mmc mmc_static, which wasted about 360 bytes. Furthermore, since MMC tiny supports only one controller at all times, get rid of mallocating the ext csd backup and replace it with static array. All in all, this patch saves ~4 kiB of bloat from the MMC core, which on platforms with severe limitations can be beneficial. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup checkpatch.pl style warnings] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-11mmc: zynq_sdhci: Add support for SD3.0Siva Durga Prasad Paladugu
This patch adds support of SD3.0 for ZynqMP. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: sdhci: Read capabilities register1 and update host capsSiva Durga Prasad Paladugu
This patch reads the capabilities register1 and update the host caps accordingly for mmc layer usage. This patch mainly reads for UHS capabilities inorder to support SD3.0. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: sdhci: Invoke platform specific tuning and delay routinesSiva Durga Prasad Paladugu
This patch adds support to invoke any platform specific tuning and delay routines if available. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: sdhci: Handle execute tuning command in sdhci_send_commandSiva Durga Prasad Paladugu
This patch upadted sdhci_send_command to handle execute tuning command. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: sdhci: Add support for disabling clockSiva Durga Prasad Paladugu
This patch adds support to disable clock if clk_disable was set and then enable or set clock if the clock was changed or clock was disabled when clock needs to be enabled. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11mmc: Changed the datatype of the variable to handle 64-bit archVipul Kumar
This patch changed the datatype of variable "start" from uint to ulong to work properly on 64-bit machines as well. Also the return type of get_timer() function is ulong. Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-08dm: mmc: socfpga: call dwmci_probe()Patrick Bruenn
On a socfpga_cyclone5 based board the SD card, was never powered up. For other dw_mmc based SoCs dwmci_probe() is called in the platform specific probe(). It seems this call is missing for socfpga_dw_mmc. With this change DWMCI_PWREN is set by dmwci_init(). Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-05-08mmc: Kconfig: add the MMC_TRACE config in KconfigJaehoon Chung
Add the MMC_TRACE config in Kconfig. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-05-08mmc: add the debug message in mmc_set_clockJaehoon Chung
Add the debug message for checking the mmc clock status. It's helpful to debug the controlling clock. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-05-08mmc: add the MMC_CLK_ENABLE/DISABLE macro in mmc.hJaehoon Chung
mmc_set_clock() function has the disable argument as bool type. When mmc_set_clock is called, it might be passed to "true" or "false". But it's too confusion whether clock is enabled or disabled with only "true" and "false". To prevent the confusion, replace to MMC_CLK_ENABLE/DISABLE macro from true/false. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-02mmc: zynq_sdhci: use correct quirk if CONFIG_ZYNQ_HISPD_BROKEN is definedHannes Schmelzer
The 'SDHCI_QUIRK_NO_HISPD_BIT' is used wrong here. The purpose of this quirk is to tell the sdhci-driver that the IP-core doesn't have a "high- speed-enable" bit in its registers. With this commit we change this to the correct quirk: SDHCI_QUIRK_BROKEN_HISPD_MODE Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2018-05-02mmc: sdhci: add SDHCI_QUIRK_BROKEN_HISPD_MODEHannes Schmelzer
Some IP-core implementations of the SDHCI have different troubles on the silicon where they are placed. On ZYNQ platform for example Xilinx doesn't accept the hold timing of an eMMC chip which operates in High-Speed mode and must be forced to operate in non high-speed mode. To get rid of this "SDHCI_QUIRK_BROKEN_HISPD_MODE" is introduced. For more details about this refer to the Xilinx answer-recor #59999 https://www.xilinx.com/support/answers/59999.html This commit: - doesn't set HISPD bit on the host-conroller - reflects this fact within the host-controller capabilities Upon this the layer above (mmc-driver) can setup the card correctly. Otherwise the MMC card will be switched into high-speed mode and causes possible timing violation on the host-controller side. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2018-05-02mmc: fix return value check conditionPeng Fan
sd_read_ssr returns 0, means no error. Fixes: 5b2e72f32721484("mmc: read ssr only if MMC write support is enabled") Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-04-30Merge git://git.denx.de/u-boot-sunxiTom Rini
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-25sunxi: improve throughput in the sunxi_mmc driverPhilipp Tomsich
Throughput tests have shown the sunxi_mmc driver to take over 10s to read 10MB from a fast eMMC device due to excessive delays in polling loops. This commit restructures the main polling loops to use get_timer(...) to determine whether a (millisecond) timeout has expired. We choose not to use the wait_bit function, as we don't need interruptability with ctrl-c and have at least one case where two bits (one for an error condition and another one for completion) need to be read and using wait_bit would have not added to the clarity. The observed speedup in testing on a A31 is greater than 10x (e.g. a 10MB write decreases from 9.302s to 0.884s). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-04-23mmc: Staticize sd_select_bus_widthMarek Vasut
Staticize the function since it's only used in mmc.c . Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Tom Rini <trini@konsulko.com>
2018-04-23Merge git://git.denx.de/u-boot-uniphierTom Rini
2018-04-24mmc: uniphier-sd: skip clock set-up for SPLMasahiro Yamada
The size of SPL is hitting the limit (64KB) for uniphier_v7_defconfig. When booting from SD/eMMC, obviously its clock has been properly set up by the boot ROM. Acutually, no need to re-initialize the clock in SPL. Using a clock driver would generalize the SoC specific code, but solving the memory footprint problem would win. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-24mmc: tmio: move clk_enable() to each driver's probe functionMasahiro Yamada
I need to differentiate the clock handling for uniphier-sd. Move it to each driver's probe function from the tmio common code so that renesas-sdhi will not be affected. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-23mmc: avoid division by zero in meson_mmc_config_clockHeinrich Schuchardt
The Odroid C2 fails to read from mmc with U-Boot v2018.03. The change avoids a division by zero. The fix was suggested by Jaehoon in https://lists.denx.de/pipermail/u-boot/2018-January/318577.html Reported-by: Vagrant Cascadian <vagrant@debian.org> Suggested-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Vagrant Cascadian <vagrant@debian.org>
2018-04-23sunxi: mmc: Fix phase delaysStefan Mavrodiev
U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where PLL5 is used, with clock rates respectively 600MHz and 768MHz. Thus there are different phase degree steps - 24 for the kernel and 30 for u-boot. In the kernel driver the phase is set 90 deg for output and 120 for sample. Dividing by 30 will result values 3 and 4. Those are the values set in the u-boot driver. However, the condition defining delays is wrong. MMC core driver requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but phase is set 30 deg for output and 120 deg for sample. Apparently this works for most cards. On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains about it. Maybe there is other boards with similar problem? So the fix is to match delays for both u-boot and kernel. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-21mmc: sh_mmcif: Add Kconfig entryMarek Vasut
Add Kconfig entry for SH MMCIF driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2018-04-21mmc: sh_mmcif: Add DM and DT probing supportMarek Vasut
Add MMC DM and DT probing support into the SH MMCIF driver. This patch abstracts out the common bits of the send command and set ios functions, so they can be used both by DM and non DM setups and adds the DM probe support. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2018-04-17mmc: mv_sdhci: zero out sdhci_host structureMatt Pelland
The mv_sdhci driver was not zeroing the sdhci_host structure it allocates causing random access violations in parts of the mmc core where the "ops" member pointers are checked and called if not NULL. Signed-off-by: Matt Pelland <mpelland@starry.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-04-14mmc: tmio: Rename Matsushita to TMIOMarek Vasut
Synchronize the naming with Linux, call the common code TMIO. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: renesas-sdhi: Wait after reconfiguring pinsMarek Vasut
The IP requires some time to recuperate after the IO pin properties were changed. Add a delay to assure this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Add missing elseMarek Vasut
Fix minor rebase omission, the else was missing which triggered two accesses to the register on 64bit variant of the IP. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Wait for command completionMarek Vasut
Make sure to wait for the command to complete altogether, including the trailing 8 clock cycles. This prevents the driver for accidentally writing the CMD register too fast before the previous command fully completed. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Correctly set mode in 16bitMarek Vasut
The HOST_MODE register must be set to 0 when the IP is operated in 16bit mode, otherwise 16bit access to the data FIFO may fail. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Special case only select registers in 16bitMarek Vasut
There are only a few registerse used in the 16bit mode which are 32bit internally. Special-case only those in the IO accessors and always write both halves. Any other register access is protected from accidentally overwriting neighboring register. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: renesas-sdhi: Add Renesas SDR104/HS200 tuning supportMarek Vasut
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Export register access functionsMarek Vasut
Export the matsu_sd_{read,write}l() common register access functions, so that they can be used by other drivers sharing the common code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Properly handle pin voltage configurationMarek Vasut
Factor out the regulator handling into set_ios and add support for selecting pin configuration based on the voltage to support UHS modes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Always check controller versionMarek Vasut
Handle the controller version even if quirks are set. The controller in Renesas Gen3 SoCs does provide the version register, which indicates a controller v10 and the controller does support internal DMA and /1024 divider. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Handle bus width 0Marek Vasut
Handle bus width 0 as 1-bit bus to assure valid content of MATSU_SD_OPTION register WIDTH field. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Handle DMA completion flag differencesMarek Vasut
The DMA READ completion flag position differs on Socionext and Renesas SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on them. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Handle Renesas div-by-1Marek Vasut
On the Renesas version of the IP, the /1 divider is realized by setting the clock register [7:0] to 0xff instead of setting bit 10 of the register. Check the quirk and handle accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Add Renesas RCar quirksMarek Vasut
Add a quirk to identify that the controller is Renesas RCar variant of the Matsushita SD IP and another quirk indicating it can support Renesas RCar HS200/HS400/SDR104 modes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: matsushita-common: Use mmc_of_parse()Marek Vasut
Drop the ad-hoc DT caps parsing in favor of common framework function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: renesas-sdhi: Handle 16bit IPMarek Vasut
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants of the IP. There is no DT property which allows discerning those, so what Linux does is it checks the size of the register area and if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle the distinction the same way. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: uniphier: Allow passing quirks to the probe functionMarek Vasut
Certain instances of the SD IP require more elaborate digging in the DT to figure out which variant of the SD IP is in use. Allow explicit passing of the quirks into the probe function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: uniphier: Add support for 16bit variantMarek Vasut
Add support for 16bit mutation of the Matsushita SD IP. Since some registers are internally 32bit, the matsu_sd_{read,write}l() has to special-case this 16bit variant a bit. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: uniphier: Drop useless checkMarek Vasut
Drop useless check in matsu_sd_{read,write}q(), this is only ever called to read the data from FIFO and only when 64bit variant of the block is used anyway. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: uniphier: Factor out FIFO accessorsMarek Vasut
Add macros to generate the FIFO accessors, since the code is almost the same with only minor differences. This is done in preparation for adding 16bit variant of the IP. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: renesas-sdhi: Add Renesas SDHI Kconfig entryMarek Vasut
Add Kconfig entry for the Renesas SDHI variant of the controller and split the Makefile entries accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11mmc: uniphier: Split out SoC specific bits from the driverMarek Vasut
Factor out common code from the uniphier SD driver, change the prefix of the functions from uniphier_sd_ to matsu_sd_ and create separate renesas-sdhi.c driver. Thus far, all the code is still compiled when CONFIG_UNIPHIER_MMC is selected and there is no functional change. This patch is a preparation for further split of the SoC specific parts of the Matsushita SD driver, used both on Uniphier and R-Car. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08treewide: Migrate CONFIG_FSL_ESDHC to KconfigMario Six
Migrate the CONFIG_FSL_ESDHC option to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>