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path: root/drivers/mtd/spi/spi-nor-ids.c
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2020-09-24mtd: spi-nor-ids: add support for Macronix mx25u12835f flashVladimir Vid
Some of Marvell A3700 boards use mx25u12835f, specifically uDPU and ESPRESSObin v7. Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> [a.heider: adapt commit message to mainline] Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-05-11sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters arrayYe Li
On i.mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters and IDs to flash parameter array. Otherwise, the flash probe will fails. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-04-30mtd: spi-nor-ids: Add Spansion s25fs512s flash entryKuldeep Singh
Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on various platforms as former is not present. Add the entry. Linux already has both the flashes present. A snippet below: { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...}, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...}, Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-30mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256Jagan Teki
IS25WP256 flash chips do support 4byte address opcodes, so enable support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-29mtd: spi-nor: Enable dual and quad read for s25fl256s0Bacem Daassi
The s25fl256s0 supports dual and quad read like s25fl256s1. Enable it by adding SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ flags to the flash_info entry. Tested on real silicon and confirmed to be working. Signed-off-by: Bacem Daassi <Bacem.Daassi@cypress.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-29mtd: spi-nor-ids: Enable SPI_NOR_OCTAL_READ flag for mt35xu*Kuldeep Singh
Commit 658df8bd9464 ("mtd: spi-nor-core: Add octal mode support") enables octal mode(1-1-8) support in spi-nor framework. mt35xu512aba and mt35xu02g supports SINGLE and OCTAL I/O. Hence, enable SPI_NOR_OCTAL_READ flag for these flashes. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-02mtd: spi: Add Macronix MX25U3235F deviceTom Warren
Add Macronix MX25U3235F flash device description. This is a 4MiB part. Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-12-18mtd: spi-nor: ids: Add GigaDevice gd25q128Peter Robinson
Add gd25q128 128Mbit chip to spi-nor id table. Tested on Pinebook Pro Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi-nor-ids: Add support for Adesto AT25SL321Fabio Estevam
Add an entry for the Adesto AT25SL321 SPI NOR chip. This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entryVignesh Raghavendra
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi-nor: spi-nor-ids: Add entries for mt25q variantsVignesh Raghavendra
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*Vignesh Raghavendra
Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with ↵Vignesh Raghavendra
SPI_FLASH_USE_4K_SECTORS U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS. Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25mtd: spi-nor: ids: Add is25wp256 chipJagan Teki
Add is25wp256, chip to spi-nor id table. Tested on SiFive FU540 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-16mtd: spi-nor: enable protection ops for SST26 flash seriesEugeniy Paltsev
Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) performs switch from previous 'spi_flash' infrastructure without proper testing/investigations which results in a regressions for SST26 flash series. Enable protection ops for SST26 flash series which were previously enabled by Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs protection ops) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-22mtd: spi: Add micron mt35xu512aba and mt35xu02g flash IDAshish Kumar
mt35xu512aba and mt35xu02g suports Single I/O and OCTAL I/O also enable use of SPI_NOR_4B_OPCODES. These flashes are tested on LX2160ARDB and LS1028ARDB respectively Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [jagan: suffix 'ba' on part name and update commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-18mtd: spi: Add flash property for Micron mt25qu512aAshish Kumar
mt25qu512a is rebranded after its spinoff from STM, so it is different only in term of extended jedec ID, initial JEDEC id is same as that of n25q512a.In order to avoid any confussion with respect to name new entry is added. This flash is tested for Single I/O mode on LS1046FRWY although it also support QUAD I/O. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12mtd: spi-nor-ids: Add Gigadevice gd25lq128 IDNeil Armstrong
This adds support for the Gigadevice gd25lq128 ID needed on the upcoming libretech-ac board. SPI_NOR_QUAD_READ is not set since it has not been tested in Quad mode. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12mtd: spi: Add Macronix MX66U2G45F deviceMarek Vasut
Add Macronix MX66U2G45F flash device description. This is a 256 MiB part. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Vignesh R <vigneshr@ti.com> [jagan: use 'g' instead of 'f' in flash name] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-12mtd: add spi flash id s25fl064lHeiko Schocher
Add support for SPANSION s25fl064l Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Vignesh R <vigneshr@ti.com>
2019-02-07mtd: spi: Add lightweight SPI flash stack for SPLVignesh R
Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
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