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path: root/drivers/mtd
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2018-09-19fix: nand: pxa3xx: Add WA for eliminating flash ready timeoutDavid Sniatkiwicz
add delay before processing the status flags in pxa3xx_nand_irq(). Signed-off-by: David Sniatkiwicz <davidsn@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> c: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19nand: pxa3xx: Add support for 8KB page 4 and 8 bit ECC NANDKonstantin Porotchkin
Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI). Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19nand: pxa3xx: cosmetic: add comments to the timing layout structuresKonstantin Porotchkin
Add comments with timing parameter names and some details about nand layout fileds. Remove unneeded definition. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19fix: nand: Replace hardcoded page chunk size with calculated oneKonstantin Porotchkin
Replace the hardcoded value of page chink with value that depends on flash page size and ECC strength. This fixes nand access errors for 2K page flashes with 8-bit ECC. Move the initial flash commannd function assignment past the ECC structures initialization for eliminating usage of hardcoded page chunk size value. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx: add support for Toshiba flashKonstantin Porotchkin
Add timings and device ID for Toshiba TC58NVG1S3HTA00 flash Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx: add support for 2KB 8-bit flashVictor Axelrod
Add support for 2KB page 8-bit ECC strength flash layout Signed-off-by: Victor Axelrod <victora@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx: Fix READOOB implementationBoris Brezillon
In the current driver, OOB bytes are accessed in raw mode, and when a page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the driver must read the whole spare area (64 bytes in case of a 2k page, 16 bytes for a 512 page). The driver was only reading the free OOB bytes, which was leaving some unread data in the FIFO and was somehow leading to a timeout. We could patch the driver to read ->spare_size + ->ecc_size instead of just ->spare_size when READOOB is requested, but we'd better make in-band and OOB accesses consistent. Since the driver is always accessing in-band data in non-raw mode (with the ECC engine enabled), we should also access OOB data in this mode. That's particularly useful when using the BCH engine because in this mode the free OOB bytes are also ECC protected. Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support") Cc: stable@vger.kernel.org Reported-by: Sean Nyekjær <sean.nyekjaer@prevas.dk> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: add support for partial chunksOfer Heifetz
This commit is needed to properly support the 8-bits ECC configuration with 4KB pages. When pages larger than 2 KB are used on platforms using the PXA3xx NAND controller, the reading/programming operations need to be split in chunks of 2 KBs or less because the controller FIFO is limited to about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to this requirement, the data layout on NAND is a bit strange, with ECC interleaved with data, at the end of each chunk. When a 4-bits ECC configuration is used with 4 KB pages, the physical data layout on the NAND looks like this: | 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC | So the data chunks have an equal size, 2080 bytes for each chunk, which the driver supports properly. When a 8-bits ECC configuration is used with 4KB pages, the physical data layout on the NAND looks like this: | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC | So, the spare area is stored in its own chunk, which has a different size than the other chunks. Since OOB is not used by UBIFS, the initial implementation of the driver has chosen to not support reading this additional "spare" chunk of data. Unfortunately, Marvell has chosen to store the BBT signature in the OOB area. Therefore, if the driver doesn't read this spare area, Linux has no way of finding the BBT. It thinks there is no BBT, and rewrites one, which U-Boot does not recognize, causing compatibility problems between the bootloader and the kernel in terms of NAND usage. To fix this, this commit implements the support for reading a partial last chunk. This support is currently only useful for the case of 8 bits ECC with 4 KB pages, but it will be useful in the future to enable other configurations such as 12 bits and 16 bits ECC with 4 KB pages, or 8 bits ECC with 8 KB pages, etc. All those configurations have a "last" chunk that doesn't have the same size as the other chunks. In order to implement reading of the last chunk, this commit: - Adds a number of new fields to the pxa3xx_nand_info to describe how many full chunks and how many chunks we have, the size of full chunks and partial chunks, both in terms of data area and spare area. - Fills in the step_chunk_size and step_spare_size variables to describe how much data and spare should be read/written for the current read/program step. - Reworks the state machine to accommodate doing the additional read or program step when a last partial chunk is used. This commit is taken from Linux: 'commit c2cdace755b' ("mtd: nand: pxa3xx_nand: add support for partial chunks") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: pxa3xx_nand: Simplify pxa3xx_nand_scanOfer Heifetz
This commit simplifies the initial configuration performed by pxa3xx_nand_scan. No functionality change is intended. This commit is taken from Linux: 'commit 154f50fbde53' ("mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: pxa3xx_nand: Fix initial controller configurationOfer Heifetz
The Data Flash Control Register (NDCR) contains two types of parameters: those that are needed for device identification, and those that can only be set after device identification. Therefore, the driver can't set them all at once and instead needs to configure the first group before nand_scan_ident() and the second group later. Let's split pxa3xx_nand_config in two halves, and set the parameters that depend on the device geometry once this is known. This commit is taken from Linux: 'commit 66e8e47eae65' ("mtd: pxa3xx_nand: Fix initial controller configuration") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: pxa3xx_nand: Increase the initial chunk sizeOfer Heifetz
The chunk size represents the size of the data chunks, which is used by the controllers that allow to split transferred data. However, the initial chunk size is used in a non-split way, during device identification. Therefore, it must be large enough for all the NAND commands issued during device identification. This includes NAND_CMD_PARAM which was recently changed to transfer up to 2048 bytes (for the redundant parameter pages). Thus, the initial chunk size should be 2048 as well. On Armada 370/XP platforms (NFCv2) booted without the keep-config devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM command: [..] pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device pxa3xx-nand f10d0000.nand: Wait time out!!! nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38 nand: Micron MT29F8G08ABABAWP nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224 This commit is taken from Linux: 'commit c7f00c29aa8' ("mtd: pxa3xx_nand: Increase the initial chunk size") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19nand: pxa3xx: Increase READ_ID buffer and make the size staticOfer Heifetz
The read ID count should be made as large as the maximum READ_ID size, so there's no need to have dynamic size. This commit sets the hardware maximum read ID count, which should be more than enough on all cases. Also, we get rid of the read_id_bytes, and use a macro instead. This commit is taken from Linux: 'commit b226eca2088' ("nand: pxa3xx: Increase READ_ID buffer and make the size static") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx-nand: fix random command timeoutsOfer Heifetz
When 2 commands are submitted in a row, and the second is very quick, the completion of the second command might never come. This happens especially if the second command is quick, such as a status read after an erase This patch is taken from Linux: 'commit 21fc0ef9652f' ("mtd: nand: pxa3xx-nand: fix random command timeouts") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: fix early spurious interruptOfer Heifetz
When the nand is first probe, and upon the first command start, the status bits should be cleared before the interrupts are unmasked. This commit is taken from Linux: 'commit 0b14392db2e' ("mtd: nand: pxa3xx_nand: fix early spurious interrupt") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: sync pxa3xx_nand_set_sdr_timing()Ofer Heifetz
Since the pxa3xx_nand driver was added there has been a discrepancy in pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min. This brings us into line with the current Linux code. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: use nand_to_mtd()Ofer Heifetz
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the one that is already part of struct nand_chip. This brings us in line with current U-boot and Linux conventions. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19mtd: nand: pxa3xx_nand: Increase initial buffer sizeOfer Heifetz
The initial buffer is used for the initial commands used to detect a flash device (STATUS, READID and PARAM). ONFI param page is 256 bytes, and there are three redundant copies to be read. JEDEC param page is 512 bytes, and there are also three redundant copies to be read. Hence this buffer should be at least 512 x 3. This commits rounds the buffer size to 2048. This commit is taken from Linux: 'commit c16340973fcb64614' ("nand: pxa3xx: Increase initial buffer size") Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-10mtd: nand: denali: fix unaligned cache operations on ARMv7 SoCsMasahiro Yamada
If the OOB size is not multiple of the cache line size, the ARMv7 cache operation still prints "Misaligned operation at range". => nand info Device 0: nand0, sector size 256 KiB Page size 4096 b OOB size 224 b Erase size 262144 b subpagesize 4096 b options 0x00104200 bbt options 0x00060000 => nand dump 0 CACHE: Misaligned operation at range [9fb15280, 9fb16360] CACHE: Misaligned operation at range [9fb15280, 9fb16360] CACHE: Misaligned operation at range [9fb15280, 9fb16360] CACHE: Misaligned operation at range [9fb15280, 9fb16360] ... The cache flushing operations won't happen in this case to cover all of the range to fix this by making sure we have things aligned. Reported-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Reword the commit message to be clear this is a direct problem rather than just a warning]
2018-08-13Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2018-08-10mtd: nand: fsl_ifc: Fix handling of bitflips in erased pagesDarwin Dingel
This is a fix made for the fsl_ifc_nand driver on linux kernel by Pavel Machek and is applied to uboot. It is currently on applied on linux-mtd. https://patchwork.kernel.org/patch/9758117/ IFC always raises ECC errors on erased pages. It is only ignored when the buffer is checked for all 0xFF by is_blank(). The problem is a single bitflip will cause is_blank() and then mtd_read to fail. The fix makes use of nand_check_erased_ecc_chunk() to check for empty pages instead of is_blank(). This also makes sure that reads are made at ECC page size granularity to get a proper bitflip count. If the number of bitflips does not exceed the ECC strength, the page is considered empty and the bitflips will be corrected when data is sent to the higher layers (e.g. ubi). Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz> Cc: Pavel Machek <pavel@denx.de> Cc: Scott Wood <oss@buserror.net> Acked-by: Pavel Machek <pavel@denx.de> [Kurt: Replaced dev_err by printf due to compiler warnings] Tested-by: Kurt Kanzenbach <kurt@linutronix.de> Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de> Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-06spi: Kconfig: Create ISSI Kconfig entryMichal Simek
Add ISSI to Kconfig to make it selectable via menuconfig. Also convert all current platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-04Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2018-08-03mtd: add spi flash id s25fl128lClément Laigle
Add support for SPANSION s25fl128l Signed-off-by: Clément Laigle <c.laigle@catie.fr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: fixed , at the end of } ] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31mtd: nand: sunxi: Return on set_feature only when not ENOTSUPPMylène Josserand
Return the error code of the set_features function only if the error code is not ENOTSUPP. Otherwise, if this function is not supported, it will return and fail to initialize the NAND. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-07-31mtd: nand: nand_base: Convert EINVAL into ENOTSUPPMylène Josserand
Convert the EINVAL error into ENOTSUPP when the GET/SET_FEATURES is not supported. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
2018-07-25mtd: nand: denali: correct buffer alignment for DMA transferMasahiro Yamada
The NAND framework makes sure to pass in the buffer with at least chip->buf_align alignment. Currently, the Denali NAND driver only requests 16 byte alignment. This causes unaligned cache operations for the DMA transfer. [Error Example] => nand read 81000010 0 1000 NAND read: device 0 offset 0x0, size 0x1000 CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] CACHE: Misaligned operation at range [81000010, 81001010] 4096 bytes read: OK Reported-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-23Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini
trini: Update colibri-imx6ull to use Kconfig for mtdparts related options. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-23mtd: nand: mxs_nand: add device tree support for i.MX 6Stefan Agner
Support i.MX 6 NAND GPMI driver data from device tree. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-22Convert CONFIG_MTD_PARTITIONS et al to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_MTD_PARTITIONS CONFIG_MTD_DEVICE Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-21Convert CONFIG_NAND_DAVINCI to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_NAND_DAVINCI Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-21Convert CONFIG_NAND_ATMEL to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_NAND_ATMEL Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-21Convert CONFIG_NAND_LPC32XX_SLC to KconfigAdam Ford
This converts the following to Kconfig: CONFIG_NAND_LPC32XX_SLC Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-16sf: add paired dev info for winbond w25q16jvLudwig Zenz
This commit adds paired dev info for winbond w25q16jv (tested w25q16jvssiq with a i.mx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16sf: add Macronix mx25l1633e entryLudwig Zenz
Add support for the Macronix mx25l1633e nor flash. (Tested on a imx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16sf: add Gigadevice gd25q16c entryLudwig Zenz
Add support for the Gigadevice gd25q16c nor flash. (Tested on a imx6 board) Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-16spi_flash: add a bunch of winbond flashes to id-tableHannes Schmelzer
This commit adds the following flashes to the id-table - W25Q16JV - W25Q32JV - W25Q64JV - W25Q128JV - W25Q256JV Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-07-09dm: spi: Update sandbox SPI emulation driver to use ofnodeSimon Glass
Update the parameters sandbox_sf_bind_emul to support livetree. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-07-02Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2018-06-28sf: Enable FSR polling on N25Q256(A)Marek Vasut
The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@openedev.com> Cc: Tom Rini <trini@konsulko.com>
2018-06-28Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2018-06-27Merge git://git.denx.de/u-boot-imxTom Rini
2018-06-27mtd: nand: mxs_nand_spl: add mxs_flash_full_identJörg Krause
For now, the existing SPL MXS NAND driver only supports to identify ONFi-compliant NAND chips. In order to allow identifying non-ONFi-compliant chips add `mxs_flash_full_ident()` which uses the `nand_get_flash_type()` functionality from `nand_base.c` to lookup for supported NAND chips in the chip ID list. For compatibility reason the full identification support is only available if the config option `CONFIG_SPL_NAND_IDENT` is enabled. The lookup was tested on a custom i.MX6ULL board with a Toshiba TC58NVG1S3HTAI0 NAND chip. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2018-06-27mtd: nand: mxs_nand_spl: refactor mxs_flash_identJörg Krause
The existing `mxs_flash_ident()` is limited to identify ONFi compliant NAND chips only. In order to support non-ONFi NAND chips refactor the function and rename it to `mxs_flash_onfi_ident()`. A follow-up patch will add `mxs_flash_full_ident()` which allows to use the chip ID list to lookup for supported NAND flashs. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2018-06-27spl, nand: add option CONFIG_SPL_NAND_IDENT to lookup for supported NAND chipsJörg Krause
Add the config option `CONFIG_SPL_NAND_IDENT` for using the NAND chip ID list to identify the NAND flash in SPL. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2018-06-27mtd: nand: export nand_get_flash_type functionJörg Krause
`nand_get_flash_type()` allows identification of supported NAND flashs. The function is useful in SPL (like mxs_nand_spl.c) to lookup for a NAND flash (which does not support ONFi) instead of using nand_simple.c and hard-coding all required NAND parameters. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2018-06-27mtd: nand: mxs_nand: add support for specific ECC strengthStefan Agner
Add support for specified ECC strength/size using device tree properties nand-ecc-strength/nand-ecc-step-size. This aligns behavior with the mainline driver, such that: - If fsl,use-minimal-ecc is requested it will use data from data sheet/ONFI. If this is not available the driver will fail. - If nand-ecc-strength/nand-ecc-step-size are specified those value will be used. - By default maximum possible ECC strength is used Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: add device tree supportStefan Agner
Support driver data from device tree. Also support fsl,use-minimal-ecc similar to Linux' GPMI NAND driver. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: move structs into header fileStefan Agner
Move structs into header file so we can use a separate compile unit for device tree support. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: add use_minimum_ecc to structStefan Agner
Add use_minimum_ecc as struct mxs_nand_info field in preparation for device tree support. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27mtd: nand: mxs_nand: separate board/controller initStefan Agner
In preparation for device tree support separate board init from controller init similar to other raw NAND drivers. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>